[PCB_FORUM] Re: Where is package to package constraint set?

 Austin, Sure, no problem mon, you're welcome. Just remember, you still
have proper feedback in the move mode, but it is the traditional DRC
flag feedback. I try to offer a helpful pointer once in a while, just
like many of us do on this ICU forum exchange. Sometimes I am too busy
to keep close tabs. But I just have to chime in when the proper tool
functionality may not be properly understood with partial Q&As.

As is true with the major CAD tools, the EE/PCB ECAD users are typically
forced to deal with compromises from ideal tool utilization until
Cadence/other EDA tool developers implement the fix voluntarily or
enough people rally around a specific change for the
disfuntionality/feature/'it is the way it works",  mechanism to be the
enhanced version of tool funtionality.

In the meantime, simply use the place manually mode of operation to tap
into the heads-up display feature. If you find that you must use the
Move command to get things repositioned per your needs, stretch etch,
multiple components, etc.,  the DFA checking still works, just fine and
dandee, but you will get the DRC flags for a violation, just like the
tool has always worked, post didge.

Yes, this has been a peeve of mine for a while too, but I am picking my
battles on some more pertinent tool enhancements. That's the best I can
do to help drive innovative changes: for example the enhanced Constraint
areas (use model) and physical rules management within CM and better
checking for same-net via structures, better alignment with
Allegro-Specctra, and the list goes on.  But we should never stop being
vocal about possible improvements on this forum because Cadence
personnel do monitor this channel.  :)


Sincerely yours, 

Michael Baumstark 

Sr. Staff Electrical Engineer / PCB Design, CID+ 
Motorola - Advanced Product Technology Center 
8000 West Sunrise Blvd.  Mail Stop: 8E8 
Plantation, FL USA 33322-9947 
Intra: http://rprc.mot.com  ; http://pcbadvisor.mot.com 
web: http://www.motorola.com 
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Motorola Internal Use                      [      ] 
Motorola Confidential Proprietary    [      ] 



-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Austin Franklin
Sent: Friday, March 21, 2008 4:26 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Where is package to package constraint set?

Hi Michael,

Thank you VERY much for the nicely detailed explanation.  It was very
clear and I believe I actually understood it.  Not having any feedback
in move mode is a problem.  I could turn on all the boxes, and visually
use them, I guess.

Regards,

Austin

> -----Original Message-----
> From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
> [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx]On Behalf Of Baumstark
> Michael-EMB043
> Sent: Friday, March 21, 2008 11:06 AM
> To: icu-pcb-forum@xxxxxxxxxxxxx
> Subject: [PCB_FORUM] Re: Where is package to package constraint set?
>
>
>  Austin,
>
> Cadence Allegro Editor supports two modes of component spacing rules 
> checks. The traditional mode uses only the packages' Place_bound  (top

> and/or bottom). When the Package to Package rule check is turned on 
> under the setup constraints GUI you can have DRC checking on for this 
> use model. As we know this checks to tangency or encroachment of the 
> place bound shapes, or allows encroachment providing there exists 
> sufficient cavity space under a component, using the
Package_height_min.
> for constraining the cavity space. But that requires a higher order of

> DFA awareness beyond the basics of the normal pick and place 
> clearances for assemblies. Most companies have tailored their 
> place-bounds to function acceptably with this simplistic mode.
>
> The second mode of checking has been around for a few years with 
> Cadence and it is established in the setup DFA spreadsheet GUI under 
> your setup pull-down menu. This is the more sophisticated mode of 
> operation but the right mode of tool operation when dealing with
"Design for Assembly"
> requirements typically needed for mass-production designs. This mode 
> sets up additional clearances from different component_types, with 3 
> adjustment settings: side-to-side, end-to-end and side-to-end (I 
> forgot the exact order as the numbers are listed in the matrix. This 
> rule checking is turned on within this GUI only, so don't get it 
> confused with the traditional package to package rule checking in the 
> main physical rules GUI.
>
> Additional notes: You need to have appropriate work done within your 
> library of parts to properly enable the DFA package to package 
> checking use model. For example, your footprints must have the 
> appropriate component_type=value established. Cadence established two 
> new layers called DFA_placebound_ (top and/or bottom) just for this 
> DFA implementation. But the traditional Place_bound (top/bot) features

> will be used if there does not exist features on the DFA_PLbound_t/b
layers.
> Also worthy of mention is the real time heads-up display of DRC 
> checking when using the DFA use model. A circular bubble displays when

> you are at the limit of your DFA spacing interaction and two small DRC

> flags display on the bubble once you have encroached inside that 
> limit. This heads-up display mode only works in the Place Manually 
> mode and not with the Move mode of operation. The traditional DRC 
> flags still function as usual, post click, but using a D-C flag to 
> indicate a DFA checking component spacing violation.
>
> Hopefully, this helps in the explanation of what is happening under 
> the hood just a little bit, more better, than simply being able to 
> turn the checking switch on.  :)
>
> Have a great Friday, it's a Good one.
>
>
> Sincerely yours,
>
> Michael Baumstark
>
> Sr. Staff Electrical Engineer / PCB Design, CID+ Motorola - Advanced 
> Product Technology Center 8000 West Sunrise Blvd.  Mail Stop: 8E8 
> Plantation, FL USA 33322-9947
> Intra: http://rprc.mot.com  ; http://pcbadvisor.mot.com
> web: http://www.motorola.com
> --------------^------------------^-----------------^------------------
> ^-
> -------------
>   >---^-.---                 >---^-.---                    >---^-.---
> Motorola Internal Use                      [      ]
> Motorola Confidential Proprietary    [      ]
>
>
>
> -----Original Message-----
> From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
> [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Austin 
> Franklin
> Sent: Thursday, March 20, 2008 2:47 PM
> To: icu-pcb-forum@xxxxxxxxxxxxx
> Subject: [PCB_FORUM] Where is package to package constraint set?
>
> Hi,
>
> For the life of me, I can't find where the default package to package 
> constraint is set.  Where is it set?
>
> Regards,
>
> Austin
>
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