[PCB_FORUM] Re: Where is package to package constraint set?
- From: "Gene Carman" <gcarman@xxxxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Fri, 21 Mar 2008 11:10:48 -0700
That lack of functionality in the move mode is something of a deal
killer...
I don't know about your designs, but in my world there are often many
updates and "adjustments" before the placement is dead on. These
modifications are usually done with the move command. Why they chose to
not use DFA in the move command is beyond me.
It seems like a switch in the options box would have been a better way
to handle this.
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Baumstark
Michael-EMB043
Sent: Friday, March 21, 2008 9:06 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Where is package to package constraint set?
Austin,
Cadence Allegro Editor supports two modes of component spacing rules
checks. The traditional mode uses only the packages' Place_bound (top
and/or bottom). When the Package to Package rule check is turned on
under the setup constraints GUI you can have DRC checking on for this
use model. As we know this checks to tangency or encroachment of the
place bound shapes, or allows encroachment providing there exists
sufficient cavity space under a component, using the Package_height_min.
for constraining the cavity space. But that requires a higher order of
DFA awareness beyond the basics of the normal pick and place clearances
for assemblies. Most companies have tailored their place-bounds to
function acceptably with this simplistic mode.
The second mode of checking has been around for a few years with Cadence
and it is established in the setup DFA spreadsheet GUI under your setup
pull-down menu. This is the more sophisticated mode of operation but the
right mode of tool operation when dealing with "Design for Assembly"
requirements typically needed for mass-production designs. This mode
sets up additional clearances from different component_types, with 3
adjustment settings: side-to-side, end-to-end and side-to-end (I forgot
the exact order as the numbers are listed in the matrix. This rule
checking is turned on within this GUI only, so don't get it confused
with the traditional package to package rule checking in the main
physical rules GUI.
Additional notes: You need to have appropriate work done within your
library of parts to properly enable the DFA package to package checking
use model. For example, your footprints must have the appropriate
component_type=value established. Cadence established two new layers
called DFA_placebound_ (top and/or bottom) just for this DFA
implementation. But the traditional Place_bound (top/bot) features will
be used if there does not exist features on the DFA_PLbound_t/b layers.
Also worthy of mention is the real time heads-up display of DRC checking
when using the DFA use model. A circular bubble displays when you are at
the limit of your DFA spacing interaction and two small DRC flags
display on the bubble once you have encroached inside that limit. This
heads-up display mode only works in the Place Manually mode and not with
the Move mode of operation. The traditional DRC flags still function as
usual, post click, but using a D-C flag to indicate a DFA checking
component spacing violation.
Hopefully, this helps in the explanation of what is happening under the
hood just a little bit, more better, than simply being able to turn the
checking switch on. :)
Have a great Friday, it's a Good one.
Sincerely yours,
Michael Baumstark
Sr. Staff Electrical Engineer / PCB Design, CID+
Motorola - Advanced Product Technology Center
8000 West Sunrise Blvd. Mail Stop: 8E8
Plantation, FL USA 33322-9947
Intra: http://rprc.mot.com ; http://pcbadvisor.mot.com
web: http://www.motorola.com
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Motorola Internal Use [ ]
Motorola Confidential Proprietary [ ]
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Austin Franklin
Sent: Thursday, March 20, 2008 2:47 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Where is package to package constraint set?
Hi,
For the life of me, I can't find where the default package to package
constraint is set. Where is it set?
Regards,
Austin
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