[PCB_FORUM] Via to shape clearance

Hello all,

I have the following problem. We use positive planes with dynamic shapes, the planes are split, i.e different voltages appear on one layer. There is a requirement that shape voids via by 0.3mm from the edge of via hole in the case when unconnected via pad IS REMOVED. For this reason VIA to SHAPE constraint is set to 50um (via annular ring is 250um and additional 50um is specified because constraint is analyzed from the edge of the via pad not from the edge of the hole). In general it works, but not always. There is a serious problem when via pad IS NOT REMOVED and this happens if via is located on the plane split (the via is connected to one plane but disconnected from the other). In such situation there is a danger that only 50um from via to the shape will be used (as defined in the constraint).

Do you have any suggestions how to correctly deal with such situation? There should be maximum copper on the power planes (split) and a possibility of a short must be excluded?

thanks,
Robert




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