[PCB_FORUM] Re: Via inside SMD discrete..

[[Jeff McKnight wrote:]]
> I found this on Howard Johnson's Web site
http://www.sigcon.com/Pubs/news/2_3.htm
> He seems to disagree with you.


Well, like everything in engineering, the correct and complete answer is "it
depends". Myself, like many others in the field, have a great amount of
respect for Dr. Johnson, so let's look at what he is saying:

Assumptions:
(1) Trace width/thickness/material is such that 100mil is about 1nH
(2) Via inductance is about 0.5nH
(3) Bypass cap is located parallel to the IC
(4) Solid planes are available
(5) Capacitor pad is about 1.0nH

Essentially the four-via, two-via debate comes down to minimizing
layout-induced inductance. What Dr. Johnson's letter seems to imply is that
the trace-length to fan-out the IC is zero (i.e. via-in-pad). In my
response, I did not make such an assumption because the question seemed
general in scope... and he's absolutely correct in the scenario he
describes. 

If you don't have via-in-pad available for thermal or whatever reasons, the
four-via solution is less desirable if you can reach your cap surface pad in
less than about 50mil (pretty typical for today's fine-pitch SMT technology)

Dr. Johnson's scenario implies that:
IC-80mil_track-Cap-80_mil_track-via = 3.1nH

Is inferior to 4-via via-in-pad:
IC-via via-Cap = 2.0nH

I couldn't agree more.

But the case where we discount via-in-pad:
IC-20mil_track-via via-20mil_track-Cap = 2.4nH

Versus the 2-via option in 50 mils:
IC-50mil_track-Cap-20mil_track-via = 2.2nH

Now the ground return path is a different story where basically more vias is
always better (unless it requires a significant additional fanout length, or
you via-down into a large ground return current channel, or etc... isn't
engineering fun?!). In my original reply, I understood the question just to
be about practical general approach. Most designers do not want to spent
egregious amounts of time controlling via placement, nor do they have the
space to place doubled up vias, so I suggested a simple formulaic practice.
As I'm sure Dr. Johnson would be the first to agree, sharing vias on the
ground side not only causes ground-bounce from the added inductance, but
also causes additional voltage noise (I*R) from the superimposed bypass
currents.

There are of course a number of assumptions in all of this, such as the
present of solid planes, which is not always a good assumption when thermal
relief, nearby via clearances, and other obstacles are accounted. And your
specific layout choice is often determined, not by what is perfectly ideal
in an academic sense, but by what is placeable/routable. Fanout and other
pitch constraints also impact these design practices and by extension what
is achievable in any given design. I think that it is for these reasons that
Dr. Johnson consults on internal IC design as well as boards for his
customers looking at extremely high-speed products.

But in the lesser, and more common cases, the impact of these decisions at
even moderately fast speeds is not all that significant in digital designs.

In any case, I hope I've been helpful in some small way and if there are
those who disagree perhaps we'll continue this discussion and we'll all
(myself included) learn something new.

Warm regards to all and happy holidays,
-Jonathan

Jonathan Friedman, GSR
Networked Embedded Systems Laboratory (NESL)
University of California, Los Angeles (UCLA) 


-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Jeff McKnight
Sent: Friday, December 09, 2005 12:22 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Via inside SMD discrete..

Jonathan Friedman wrote:

> It is better to route the signal across the cap than to route the cap 
> and IC to the planes independently. When routing the cap send the 
> trace from the IC into the cap pad from the opposite side as the trace 
> exits the cap pad to go to the via. If possible, performance will be 
> much improved by creating a V shape with the entry and exit traces as 
> this will turn the trace parasitic inductances and resistances in your 
> favor.
>  
> I'm a research EE who specializes in this field. If you need more info 
> on this, please feel free to contact me (jf@xxxxxxxxxxx 
> <mailto:jf@xxxxxxxxxxx>).
>  
> Warm regards to all and happy holidays, -Jonathan
>
> Jonathan Friedman, GSR
> Networked Embedded Systems Laboratory (NESL) University of California, 
> Los Angeles (UCLA)
>
>
I found this on Howard Johnson's Web site
http://www.sigcon.com/Pubs/news/2_3.htm
He seems to disagree with you.

--
Jeff McKnight
Development Engineer

Athens Technical Specialists, Inc.
8157 U.S. Route 50
Athens, Ohio
45701-9303

740.592.2874
FAX.594.2875

www.atsi-tester.com

visit ATSI's online shop:
www.atsi-tester.com/shop/ 


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