[PCB_FORUM] Re: Verilog to allegro netlist?

Hi Austin,

I was answering the question about the case where somebody gets Verilog netlist 
and
needs to go to Allegro. The question was how to bring this Verilog netlist to 
Allegro ?
One of the ways is to generate schematic from that Verilog netlist and save 
such schematic
as Concept schematic. Then somebody needs to assign PCB properties to instances
and create chips info for every part. Then the generated schematic can be taken 
to Allegro.
Schematic generation can be done through a third party like elgris.com

GenView utility is used to create a symbol that represents the  schematic.
I doubt that it generates schematics. Please tell me if I'm wrong here.

Regards




----- Original Message ----
From: Austin Franklin <allegrolist@xxxxxxxxxxxx>
To: icu-pcb-forum@xxxxxxxxxxxxx
Sent: Tuesday, April 29, 2008 6:36:12 AM
Subject: [PCB_FORUM] Re: Verilog to allegro netlist?

 
Hi 
Gary/Arimitsu,
 
The .v files are 
probably Verilog files that are created when you do a "save" if the "Create 
Netlist" check box is selected.  You can choose either Verilog or 
VHDL.  I thought Concept could use the Verilog to get to 
Allegro and that you could re-generate a schematic using the Genview 
utility?
 
Regards,
 
Austin
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx  
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx]On Behalf Of gary
Sent: Tuesday, April 29, 2008 3:38 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Verilog to  allegro netlist?


This  is a strange request. However check www.elgris.com
They have the tool that  might help.
You need to generate schematic from Verilog netlist and save  it
as ConceptHDL design.


-----  Original Message ----
From: arimitsu seiji  <arimitsus@xxxxxxxxxxx>
To: icu-pcb-forum@xxxxxxxxxxxxx
Sent:  Wednesday, April 23, 2008 4:34:20 PM
Subject: [PCB_FORUM] Verilog to  allegro netlist?

 
 Hello all,

I was wondering if anyone can help me with Concept  HDL.  I received several 
".v" file and I'm requested to use this as a  netlist for allegro.  I am not 
very experienced with HDL and I am not  able to get this file to come up with 
anything.  Is there a way to  create netlist from ".v" file?  If anyone can 
help I would greatly  appreciate your help.

Thank you in  advance.

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