[PCB_FORUM] Re: Verilog to allegro netlist?
- From: gary <rogiru@xxxxxxxxx>
- To: icu-pcb-forum@xxxxxxxxxxxxx
- Date: Tue, 29 Apr 2008 00:38:23 -0700 (PDT)
This is a strange request. However check www.elgris.com
They have the tool that might help.
You need to generate schematic from Verilog netlist and save it
as ConceptHDL design.
----- Original Message ----
From: arimitsu seiji <arimitsus@xxxxxxxxxxx>
To: icu-pcb-forum@xxxxxxxxxxxxx
Sent: Wednesday, April 23, 2008 4:34:20 PM
Subject: [PCB_FORUM] Verilog to allegro netlist?
Hello all,
I was wondering if anyone can help me with Concept HDL. I received several
".v" file and I'm requested to use this as a netlist for allegro. I am not
very experienced with HDL and I am not able to get this file to come up with
anything. Is there a way to create netlist from ".v" file? If anyone can help
I would greatly appreciate your help.
Thank you in advance.
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