[PCB_FORUM] Verilog to allegro netlist?
- From: arimitsu seiji <arimitsus@xxxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Wed, 23 Apr 2008 16:34:20 -0700
Hello all,
I was wondering if anyone can help me with Concept HDL. I received several
".v" file and I'm requested to use this as a netlist for allegro. I am not
very experienced with HDL and I am not able to get this file to come up with
anything. Is there a way to create netlist from ".v" file? If anyone can help
I would greatly appreciate your help.
Thank you in advance.
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- From: Dale Rasmusen
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- » [PCB_FORUM] Re: Verilog to allegro netlist?
- [PCB_FORUM] Propagation Rules driven from Schematic to Allegro
- From: Dale Rasmusen