[PCB_FORUM] Re: Using an "Electrical CSET" vs a "Constraint Set" for diff pairs...

Hi Gary,

> I'm not sure how to handle a different trace width and spacing within the
pair for inner layers as opposed to outer layers.

I use Setup/Constraints and under "Physical (lines/vias) rule set" I use
"Set values..." and create a new Constraint Set Name, and set the values for
each layer there.  Close that, then use "Attach property, nets..." and
assign the attribute "NET_PHYSICAL_TYPE" to all the nets I want to control
with this constraint.

That's the only way to do different trace width/gap on different layers that
I know of in Allegro 15.2.  Is that what you were asking?

Unfortunately, I don't always have the luxury of having the same width/gap
for inner and outer layers.

Regards,

Austin
  -----Original Message-----
  From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx]On Behalf Of Macindoe, Gary
  Sent: Wednesday, March 26, 2008 1:18 PM
  To: icu-pcb-forum@xxxxxxxxxxxxx
  Subject: [PCB_FORUM] Re: Using an "Electrical CSET" vs a "Constraint Set"
for diff pairs...


  Hey Austin,



  You know, I've wondered about that. Luckily I haven't had to deal with it
yet.

  One reason is that lately I only have top and bottom as routing layers.

  I think the last time I had inner layers, the stack-up was designed to
have the trace widths/spaces the same for inner and outer for all
impedances.



  Here's how I handle it now for only outer routing layers, on 15.5.1:



  -          I set up the diff pairs using Logic -> Assign Differential
Pair, Auto Generate



  -          I set the trace width, spacing etc. for the pairs in CM



  -          I create a Spacing Constraint Set for each impedance (i.e.
"90DIFF" for USB) with the "Line To Line" set to the spacing required pair
to pair



  I'm not sure how to handle a different trace width and spacing within the
pair for inner layers as opposed to outer layers.



  I would suggest, if you can, to design the stack-up to have the widths and
spacings the same for outer and inner.

  That's the easy way out!



  Maybe setting up constraints, including diff pairs, is easier in 16, I
hope so.



  Good luck, I'm curious to see if anyone has the solution to this.





  Gary E. MacIndoe
  PCB Design Engineer
  Fort Collins, Colorado

  amd.com

  gary.macindoe@xxxxxxxxxxxxxxxxxxxx Message-----
  From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Austin Franklin
  Sent: Wednesday, March 26, 2008 12:39 PM
  To: icu-pcb-forum@xxxxxxxxxxxxx
  Subject: [PCB_FORUM] Using an "Electrical CSET" vs a "Constraint Set" for
diff pairs...



  Hi,



  There appear to be two ways to get the diff pair spacing and gap, but only

  one allows differing them by layer.  Setting up an "Electrical CSET" only

  seems to allow one overall (as in for all layers) space/gap.  But, the

  advantage of using the ECSET is you can assign it to a net or multiple
nets

  using the Constraints Manager spreadsheet using a pulldown menu.



  Or, I can setup a "Constraint Set" and select each layer's space/gap...but
I

  then have to attach this as a property to each and every net manually by

  selecting the nets and attaching this Constraint Set name as a

  NET_PHYSICAL_TYPE attribute.



  I prefer the Constraint Set, since it gives me the per layer control...but

  the thing that seems to be missing, is the ability to assign a given

  Constraint Set to the nets using the Constraint Manager spreadsheet.



  I'm on 15.2.  Am I missing something?  If not, has this improved on 15.7
or

  16?



  Regards,



  Austin



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