[PCB_FORUM] Re: Total number of pages in a hierarchical design
- From: "Khurana, Varun" <vkhurana@xxxxxxxxxxxx>
- To: "icu-pcb-forum@xxxxxxxxxxxxx" <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Mon, 20 Sep 2010 12:35:58 -0700
Thanks Charlie,
That’s what I planned on using it (and in fact did you use it) but found a bug
wherein module_order.dat wouldn’t update with the new (latest) page information
upon deleting a page using Edit > Page > Delete command.
I see Christopher Shaw just replied…I think his method may work.
Varun
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Davies, Charles
(cdavies)
Sent: Monday, September 20, 2010 12:30 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Total number of pages in a hierarchical design
The recipe lies in the content of the module_order.dat file in the sch_1
directory.
Regards,
Charlie
On Sep 20, 2010, at 12:11 PM, "Khurana, Varun"
<vkhurana@xxxxxxxxxxxx<mailto:vkhurana@xxxxxxxxxxxx>> wrote:
Folks,
Is there a way to programmatically determine the total number of pages in a
hierarchical design in Allegro Design Entry HDL v16.3?
Counting page files in sch_1 folder is not an option since it won't work, if
the hierarchical symbol is instantiated more than once. Ideas are appreciated.
Thanks,
Varun
Qualcomm Inc.
San Diego, CA
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