[PCB_FORUM] Re: TestPrep
- From: "Vivekananda R K - CTD, Chennai" <vivekanandark@xxxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Thu, 28 Apr 2005 14:10:03 +0530
Yves
You set the spacing rules from setup/constraints(only from Allegro_expert)
1.open the constarint manager from setup menu
2.click the set Values from spacing rule set
3.From the Global option, select test via and set the spacing rules between
testvia to testvia,test via to pth,testvia to smd,testvia to via etc.
Hope this will solve.
Regards
K.vivek
-----Original Message-----
From: Yves Cantraine [mailto:yves@xxxxxxxxx]
Sent: Thursday, April 28, 2005 12:34 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: TestPrep
Hi all,
We have a small problem running testprep.
We have created special testvia's with larger pads on bottom.
And enabled the option to replace current via's with the test via's.
After running the auto mode, we have several nets that did not get testpads.
So we'll have to add them manually, but this implies that we'll have to
slide existing testvia's.
It seems that the spacingcheck between different testvia's is using the
design constraints and not the spacing value set in the testprep params
window.
Is there a way to have the spacing rule testvia - testvia set to a certain
value and the value between testvia - via and via - via to another ? Or is
there another way to solve this?
Thanks
Yves
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