[PCB_FORUM] Re: TestPrep
- From: "Yves Cantraine" <yves@xxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Thu, 28 Apr 2005 09:04:20 +0200
Hi all,
We have a small problem running testprep.
We have created special testvia's with larger pads on bottom.
And enabled the option to replace current via's with the test via's.
After running the auto mode, we have several nets that did not get testpads.
So we'll have to add them manually, but this implies that we'll have to
slide existing testvia's.
It seems that the spacingcheck between different testvia's is using the
design constraints and not the spacing value set in the testprep params
window.
Is there a way to have the spacing rule testvia - testvia set to a certain
value and the value between testvia - via and via - via to another ? Or is
there another way to solve this?
Thanks
Yves
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