[PCB_FORUM] Re: Test Prep parameter setup problem.
- From: "Musetti, Carl" <cmusetti@xxxxxxxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Mon, 21 Aug 2006 14:17:46 -0400
No this does not solve the problem.
________________________________
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Jean Bratton
Sent: Friday, August 18, 2006 9:09 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Test Prep parameter setup problem.
The "replace via" option is in the Testprep Parameters form. However, I
suspect that's not Carl's problem. I'm on 15.5.1 S050, and I can't
duplicate the problem. I can close the form whether this box is checked
off or not.
________________________________
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of David Kelly
(davidkel)
Sent: Friday, August 18, 2006 4:59 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Test Prep parameter setup problem.
I'm new to 15.5.1 and haven't tried test prep yet. I looked at it and
tried to duplicate what you are doing.
I had the same problem. What is missing or has been moved is "replace
via" Without this parameter
it will fail unless you are routing with the test via.
David Kelly
davidkel@xxxxxxxxx
720-562-6316
________________________________
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Musetti, Carl
Sent: Friday, August 18, 2006 1:59 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Test Prep parameter setup problem.
I have a board that is backwards the major components are on the
bottom side so we want to do the ICT test from the top of the board.
When we change the methodology layer to the top and the restriction of
allow under componenet to bottom layer only then put in our padstacks
for pins which is a top side pad of 35 and for vias it is a 12 drill 35
pad on the top side 24 pad on all other layers except planes and masks.
The minimum pad size is set to 30 whenwe go to close the form it states
that pad size is too small for vias and pins and will not close the
form. I have done this on other designs in 15.5.1 oh yeah we are on
15.5.1 S051, so it has got to be something stupid here.
What have when done wrong is there some other setting or env variable
that needs t be turned on to allow this to happen.
Thanks all in advance
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- References:
- [PCB_FORUM] Re: Test Prep parameter setup problem.
- From: Jean Bratton
- [PCB_FORUM] Re: Test Prep parameter setup problem.
Other related posts:
- » [PCB_FORUM] Test Prep parameter setup problem.
- » [PCB_FORUM] Re: Test Prep parameter setup problem.
- » [PCB_FORUM] Re: Test Prep parameter setup problem.
- » [PCB_FORUM] Re: Test Prep parameter setup problem.
- » [PCB_FORUM] Re: Test Prep parameter setup problem.
- » [PCB_FORUM] Re: Test Prep parameter setup problem.
