[PCB_FORUM] Re: Suppressing pads
- From: "Baumstark Michael-EMB043" <M.Baumstark@xxxxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Tue, 14 Sep 2010 16:15:40 -0400
BTW -
On the subject of unused pad suppression. If you are submitting CAD data
to PCB fab vendor in ODB++ format does the artwork order definition
convey the suppress unused pads into the ODB++ database, when enabled by
layer? Or is there a setting within the ODB++ export option that
controls this, by layer?
Also, Richard VanOs cited the enable unused padstack suppression option
within the Padstack editor. To my understanding, this is a switch that
will permit this particular padstack to have suppressed padstacks, but
ONLY when the directive is set to suppress in the Artwork formatting
directives. Is my understanding correct?
Sincerely yours,
Michael Baumstark
Sr. Staff Electrical Engineer / PCB Design, CID+
Motorola - EMS - Worldwide Radio Solutions -
Astro - APTC/Physical Design Organization
8000 West Sunrise Blvd. Mail Stop: 1329
Plantation, FL USA 33322-9947
Intra: http://rprc.mot.com <http://rprc.mot.com/> ;
http://pcbadvisor.mot.com <http://pcbadvisor.mot.com/>
web: http://www.motorola.com <http://www.motorola.com/>
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________________________________
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Schwartz,
Jerome
Sent: Thursday, September 09, 2010 12:41 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Suppressing pads
Hope some of you are seeing the issue I am. These are outer layer vias.
You can't suppress them and expect the vias to be plated through.
I would make them blind vias since the outer layers are foil laminated.
Jerry
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Mark Yamashita
(mayamash)
Sent: Thursday, September 09, 2010 12:31 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Suppressing pads
Gennadiy,
This is in your artwork set up. Manufacture => artwork => select
your layer. This is in the allegro expert.
Mark
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Gennadiy
Kiryukhin
Sent: Thursday, September 09, 2010 9:06 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Suppressing pads
Under Setup I have: Drawing Size, Drawing Options, Text Size, Grids,
Subclasses, Define BB Via, Constraints, Property Definitions, Define
Lists, Areas, Outlines, and User Prefs.
Is it specific to a certain version/license?
CHRIS LANZA wrote:
> Under setup there is pad suppression. You suppress vias also
>
> -----Original Message-----
> From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
> [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Gennadiy
> Kiryukhin
> Sent: Thursday, September 09, 2010 10:47 AM
> To: icu-pcb-forum@xxxxxxxxxxxxx
> Subject: [PCB_FORUM] Suppressing pads
>
> I have a BGA with ground plane under it. The problem I have is that
the
> ball pitch is too small to create a single ground (power)plane under
it
> with all the via pads unsuppressed. See picture attached. Instead of
> having one GND plane I have small islands. Is there any way to
suppress
> pads on vias that don't have connections on that plane so that I have
> more room to create a single GND plane?
>
> Thank you.
>
--
Gennadiy Kiryukhin
Development Engineer
ATSI
8157 US Route 50
Athens, OH 45701
Phone: (740) 592-2874
Fax (740) 594-2875
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