[PCB_FORUM] Re: Solder mask layer definition

I was wondering if your test vias was made as a symbol.  We usually make the test pin as a symbol that way that it is not just ordinary via.  In that case you will be able to edit the padstack for that symbol to have open soldermask.  Otherwise if they are all same vias I think you will have some pesky job ahead of you replacing just the test pin via with open soldermask or doing what Gene mentioned.  Someone else might have a better idea so good luck!

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From: "Gene Carman" <gcarman@xxxxxxxxxxxxxxx>
Reply-To: icu-pcb-forum@xxxxxxxxxxxxx
To: <icu-pcb-forum@xxxxxxxxxxxxx>
Subject: [PCB_FORUM] Re: Solder mask layer definition
Date: Wed, 13 Dec 2006 17:46:15 -0800

Not that I am aware of... especially if that test via has all the same parameters as your regular via.    But you can go and create a solder mask "dot" and simply place it where you want the solder mask removed...  means you will have to touch each and every location where you want that "feature."

-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx]On Behalf Of Eileen Ong
Sent: Wednesday, December 13, 2006 5:37 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Solder mask layer definition

Hi,

 

Right now they are defined as same via type, is there a way to global replace the test via to another via type?

 

Thanks.

 

Best regards,
Eileen

 

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From: icu-pcb-forum-bounce@xxxxxxxxxxxxx [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Gene Carman
Sent: Thursday, December 14, 2006 9:30 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Solder mask layer definition

 

You need to have different vias for that...  create the vias with the solder mask you need and then place the vias you need in the proper place in the design.

-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx]On Behalf Of Eileen Ong
Sent: Wednesday, December 13, 2006 5:09 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Solder mask layer definition

Hi,

Help will be very much appreciated; trying to figure before I release the Gerber.

 

I’m trying to set up the bottom solder mask in the artwork setting.

 

I have a standard via that are defined as test via on some locations.

 

How do I set up the artwork solder mask layer such that for test via, the solder mask is open and non test via the solder mask is close.

 

Thanks in advance.

 

Best regards,
Eileen  

 

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