[PCB_FORUM] Re: Shape won't fill



Michael.Catrambone@xxxxxxxxxx wrote: 
Kevin,

A couple things to check is:

- Is there a layer specific route
keepout were this shape is drawn ?

Nope. No route keepouts. When I delete the smaller plane
shape the larger one fills the space.


- Is there two shapes with different
net names directly on top of each other ?
Nope, same as above. 

Hope this helps,
Michael Catrambone

I just tried copying all of the shapes to another layer
and it acts the same on another layer. The small shape
still will not fill. If it is dynamic.

Thanks,
Kevin




Kevin McCowan
12/20/2004 08:08 AM


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Did. It is set to 200. By default it is set to 125.
Thanks, any other takers?

Kevin

Don.Kost@xxxxxxxxxxx wrote:

Kevin,
Try changing the "suppress shape less than" under void controls to a
smaller number.
Don ...........................

Inactive hide details for Kevin McCowanKevin McCowan


                       *Kevin McCowan*
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                       12/20/2004 07:55 AM
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[PCB_FORUM] Shape won't fill




Ok, my turn.
I have a plane layer filled with a plane.
I have cut out (or overlayed) 3 smaller plane cutouts.
2 of them are no problem. One of them refuses to fill.
When I move it off the board it fills fine, back on, empty.
I redrew it and deleted the original, same thing.
I z-copied to another layer and it filled. Z-copy it back
and empty. I haven't tried changing the net, yet.
Cadence just send out an advisory that said if this happens
move it zero and put it back down and it will fill. NOT!
I made it static and it filled. Now I need to void all of
the vias and pins. If I select all of the vias and pins
it says "error: no shape left after voiding". If I select
a small bunch of vias (20-25) and pins it works. But it
takes literally 40 minutes to complete each time.
I have a dual 3.06G xeon with 1G mem.
It is the last net in the design and I have been fighting
this *&@$%! thing for 3 days.
Any ideas?

Oh, by the way, our maintenance expired, money issues.
We'll pick it up again next year (I hope). I have not
been able to contact cadence on this due to that.

Much thanks in advance,
Kevin McCowan
Sr PCB Designer
TSI Telsys
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