Kevin,
This happened to me recently and I found that if I have a "smaller
shape" surrounded by a larger shape such as on a FPGA...
I had to make sure to convert smaller "FPGA" shapes to dynamic before
the larger surrounding shape.
If the smaller shape is static and the larger surrounding shape is
converted to dynamic, then small islands were created in the smaller
"fpga" static shape.
This was while converting older static to dynamic.
Hope this helps, Mark
Kevin McCowan wrote:
Ok, my turn. I have a plane layer filled with a plane. I have cut out (or overlayed) 3 smaller plane cutouts. 2 of them are no problem. One of them refuses to fill. When I move it off the board it fills fine, back on, empty. I redrew it and deleted the original, same thing. I z-copied to another layer and it filled. Z-copy it back and empty. I haven't tried changing the net, yet. Cadence just send out an advisory that said if this happens move it zero and put it back down and it will fill. NOT! I made it static and it filled. Now I need to void all of the vias and pins. If I select all of the vias and pins it says "error: no shape left after voiding". If I select a small bunch of vias (20-25) and pins it works. But it takes literally 40 minutes to complete each time. I have a dual 3.06G xeon with 1G mem. It is the last net in the design and I have been fighting this *&@$%! thing for 3 days. Any ideas?
Oh, by the way, our maintenance expired, money issues. We'll pick it up again next year (I hope). I have not been able to contact cadence on this due to that.
Much thanks in advance,
Kevin McCowan
Sr PCB Designer
TSI Telsys
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