[PCB_FORUM] Re: Schematic drafting practices

I guess one thing may not be clear to you guys arguing for p/g pins visible
everywhere.
These designs.. are no long field debuggable.   We're talking 1100+ pin
multi-processor/FPGA designs that a field guy can't debug.  RTOS effects
that can't be field investigated, etc...
The simple circuits on those boards?  That are debuggable? Yes, the pins are
shown.

Moral: don't apply old rules to new designs.

-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Austin Franklin
Sent: Monday, March 30, 2009 12:30 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Schematic drafting practices

Hi Alan,

Exactly!  I've also been in field service, and yes, that information is
critical, whether in a printed manual, or in PDF.  It also points out uses
for the schematics other than simply generating a netlist.  And that this
use may not entail the native tool used to draw the schematics.  Making the
schematics more useful for all the intended (and sometimes unintended)
purposes is very important, IMO.

Regards,

Austin

> -----Original Message-----
> From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
> [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx]On Behalf Of Ritter, Alan
> Sent: Monday, March 30, 2009 11:17 AM
> To: icu-pcb-forum@xxxxxxxxxxxxx
> Subject: [PCB_FORUM] Re: Schematic drafting practices
>
>
> Just out of curiosity, what about field service guys who may not
> have ready access to online (on-disc) .pdf files?  Having all
> information available in the schematic as either a table or
> explicit pinouts seems critical for field service activities.
>
> (Grated, my viewpoint is from that of a medical capital equipment
> manufacturer with a field service force, not a manufacturer of
> consumer goods that are throwaways and never "fixed" in the normal sense.)
>
> /s/jar (Alan Ritter, alan.ritter@xxxxxxxxxx)
>         http://www.mtritter.org
>
>
> Just a few comments from my side of the world. I have to use my own
> schematics in the lab as I am the EE who is forced to use his own work
> (schematics, layouts, silkscreen!!, documentation).  I *never* use the
> power/ground table nor do I use the individual pinned out symbols
> -- in the
> case where the symbol is huge (FPGA, processor).  I use PDF!  I hotlink
> everything in the lab to PDF now and have monitors around where
> online data
> (local, www) is at your fingertips.  When using OrCAD, the P/G for large
> symbols is placed as its own part with individual pins.  In Concept, the
> hidden P/G through size is used with and without the table. Tables are no
> longer generated as we find they are a waste of time. For small analog
> parts, the VCC/GND pins are individually instantiated.
>
> Over the last 25 yrs I have seen schematics change from draftsman-drawn
> blueprints to modern CAD schematics.  I know what *hands-on* guys
> are using
> in the lab.  I've managed labs. I've debugged.  I've layed out.
> I've built
> symbols.  Power and Ground needs to be your company philosophy --
> but don't
> force something on someone until YOU'VE used your own documentation RULES
> and learned the pros and cons of the rules.
>
> BD
>
>
>
>
>
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