[PCB_FORUM] Re: Schematic drafting practices

Hi Bill,

> I have to use my own
> schematics in the lab as I am the EE who is forced to use his own work
> (schematics, layouts, silkscreen!!, documentation).

Me too...and then I have to give the entire design/documentation to my
client, and it better be documented well...

> I *never* use the
> power/ground table nor do I use the individual pinned out symbols
> -- in the
> case where the symbol is huge (FPGA, processor).  I use PDF!

How do you verify that the power/ground pins are correct on the schematic if
you don't show them visibly on the schematics?  Say you're in the lab, and
there was a power/ground pinout error.  How would you find that with just a
printed copy of the schematics and the PDF of the IC?

> Over the last 25 yrs I have seen schematics change from draftsman-drawn
> blueprints to modern CAD schematics.  I know what *hands-on* guys
> are using
> in the lab.  I've managed labs. I've debugged.  I've layed out.
> I've built
> symbols.  Power and Ground needs to be your company philosophy --
> but don't
> force something on someone until YOU'VE used your own documentation RULES
> and learned the pros and cons of the rules.

I've got basically the same experience (though 31 years as an engineer) and
I agree.  My methodology has been developed over many years, and through the
many engineering groups and departments that I've worked in, started and
run.  I've been through quite a few different scenarios of this very issue,
and settled on visible pins on the schematic (any methodology) is correct
design practice.  Not showing them, IMO, is not correct design practice.

I have seen cases where not having them visible lead to errors, and made
debugging/schematic verification more difficult, and having them visible
avoided errors, and makes schematic verification easier.  It's complete
documentation IMO.

Regards,

Austin

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