[PCB_FORUM] Re: Schematic drafting practices

With today's high-pin-count devices, you're quite correct.  The old POWER_PINS 
property was nice when you were drawing individual gates of a multi-gate 
SSI/MSI package.  (I said I was a dinosaur)

Plus, using components with 100+ pins (and often 3x that or more for BGAs), you 
end up splitting the component into multiple schematic symbols just to be able 
to fan it out, so it's easy to build one section/view of the component as JUST 
the power/ground pins so they're easy to find and not spread out all over the 
place.  Worse, I can see the power/ground pin table being too much to fit on 
one page if you have a larger design with multiple BGAs.  (Our stuff is fairly 
"simple" by today's standards...maybe a high-pin-count MCU plus one big EPLD 
per board.  We're not building stuff that is anywhere near the bleeding edge in 
terms of pin counts.)

/s/jar (Alan Ritter, alan.ritter@xxxxxxxxxx)
        http://www.mtritter.org


> Regarding the power/ground pin table, if you use implicit
> power/ground pins and POWER_GROUP properties in Cadence/Concept,
> the power/ground pins may NOT be shown on the component schematic
> entities, so a table is most helpful.

Agreed, but that, IMO, is bad practice to not show all the power/ground pins
of a component on the component's symbol.

Regards,

Austin





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