[PCB_FORUM] Re: [SPAM] Re: Speeding up Allegro

I plot the screen with rats then bring that plot in on a temporary MFG
layer. This way you have locations of pins that are not connected yet.
Then I attach NO_RAT property to all GND and Power nets. Allegro will be
a lot faster.
Rosalynn

________________________________

From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Ed Hickey
Sent: Friday, February 16, 2007 8:32 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: [SPAM] Re: Speeding up Allegro


Constraint Manager can also be used to identify or edit Net Level
properties. Double-click the "No Rat" column header to sort nets based
on this property. Hopefully my graphic made it's way through the server.
If not, open CM then go to "General Properties" under the Net folder. 

Ed
 
 
 
 
 
Ed Hickey
Product Engineer - Allegro PCB Editor
Cadence Design Systems
Chelmsford, MA 01824
978-262-6545
 


________________________________

        From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Macindoe, Gary
        Sent: Friday, February 16, 2007 11:06 AM
        To: icu-pcb-forum@xxxxxxxxxxxxx
        Subject: [PCB_FORUM] Re: [SPAM] Re: Speeding up Allegro
        
        

        Jim,

         

        You can easily find all nets with a common property (i.e. No
Rat):

         

        -          click Display -> Element, "Nets" on in Find filter

        -          set Find By Name pull-down to "Property"

        -          click the More button

        -          click on "No_Rat=" from the section at left (it moves
to the Selected objects at right)

        -          click on the Apply button

        -          all of the nets with No Rat now appear in the Show
Element window

         

        Good luck with it!

         

        Gary

         

          

        Gary E. MacIndoe

        PCB Design Engineer

        Longmont, Colorado

         

        amd.com

        gary.macindoe@xxxxxxx

        
________________________________


        From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of J Wages
        Sent: Friday, February 16, 2007 8:40 AM
        To: icu-pcb-forum@xxxxxxxxxxxxx
        Subject: [PCB_FORUM] Re: [SPAM] Re: Speeding up Allegro

         

        Well, I am at the point where I need to find which power nets,
the nets which I had NO_RAT=TRUE property on before, and it's a lot
easier to see them when you can hi-lite the rats nets. Thanx anyways.

         

         

        Jim S. Wages / SR. PCB Layout Designer:  

        Cary, NC - H: 919-466-1596 Cell: 919-484-2963

         

                -----Original Message-----
                From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Dave Seymour
                Sent: Friday, February 16, 2007 10:31 AM
                To: icu-pcb-forum@xxxxxxxxxxxxx
                Subject: [SPAM] [PCB_FORUM] Re: Speeding up Allegro

                Jim,
                
                On power nets with lots of connections, 
                Add the property NO_RAT.
                
                dave
                
                
                Marcel Tran wrote:
                
                

                
                Jim, 
                
                Look for those Nets that were defined as DC nets. You
may temporarily remove this property to improve Allegro performance ...
(Logic/Identify DC nets/ ....) 
                
                Thanks and Regards,
                
                Marcel Tran C.I.D.
                IBM Corp.
                Off. 919-254-1014 
                
                

"J Wages" <jwages@xxxxxxxxx> <mailto:jwages@xxxxxxxxx>  
Sent by: icu-pcb-forum-bounce@xxxxxxxxxxxxx 

02/16/2007 09:59 AM 

Please respond to
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Subject

[PCB_FORUM] Speeding up Allegro

 

 

 

                
                
                
                Hi folks, 
                Quick question and I'm pretty sure I've seen this
subject floating around before. Allegro 15.5.1 
                I'm nearing the end of routing a very large and dense
design. I'm down to cleaning up the power signals (3.3v & gnd...etc) and
Allegro is draggin' big time. What is the easiest way to reduce the time
between mouse clicks when hooking up these large pin count nets?
Currently is about 20 seconds minimum between clicks. 
                Change the shapes from dynamic to static? I've turned
off the on-line DRC, but that didn't seem to help. I know it's probably
something really obvious, but my brain has turned to mush these last
couple days. 
                Thanx in advance. 
                  
                Jim S. Wages / SR. PCB Layout Designer:   
                Cary, NC - H: 919-466-1596 Cell: 919-484-2963 

        
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                Dave Seymour, CID+
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