[PCB_FORUM] Re: [SPAM] Re: [SPAM] Re: Speeding up Allegro
- From: "J Wages" <jwages@xxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Fri, 16 Feb 2007 11:23:13 -0500
Thanks Dave. I do all of those things you mentioned, but for the "quick
and easy" power net connection clean-up, disabling the dynamic shapes
works like a dream. The only caveat, is that any manual voids you
incorporate into any shapes in this state will not show up until you
perform the shape smooth function.
But thanks again.
Jim S. Wages / SR. PCB Layout Designer:
Cary, NC - H: 919-466-1596 Cell: 919-484-2963
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Dave Seymour
Sent: Friday, February 16, 2007 10:58 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [SPAM] [PCB_FORUM] Re: [SPAM] Re: Speeding up Allegro
I agree that it is easier to find the un-connected pins with
a rats line.
But, I try to get it down to some managable level before
removing the NO_RAT. I'll hi-lite the voltage net and
scan around for missing pins.
There is also a skill routine HL_NPE which highlights the
pins with No pin escapes. I'll zoom way out and run the skill
and use the globle window to help locate the pins.
You can also turn off all graphical layers and then turn on the rats.
This at least helps locate the pins quickly.
Hope this helps, Good luck.
Dave
J Wages wrote:
Well, I am at the point where I need to find which power nets, the nets
which I had NO_RAT=TRUE property on before, and it's a lot easier to see
them when you can hi-lite the rats nets. Thanx anyways.
Jim S. Wages / SR. PCB Layout Designer:
Cary, NC - H: 919-466-1596 Cell: 919-484-2963
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Dave Seymour
Sent: Friday, February 16, 2007 10:31 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [SPAM] [PCB_FORUM] Re: Speeding up Allegro
Jim,
On power nets with lots of connections,
Add the property NO_RAT.
dave
Marcel Tran wrote:
Jim,
Look for those Nets that were defined as DC nets. You may temporarily
remove this property to improve Allegro performance ... (Logic/Identify
DC nets/ ....)
Thanks and Regards,
Marcel Tran C.I.D.
IBM Corp.
Off. 919-254-1014
"J Wages" <mailto:jwages@xxxxxxxxx> <jwages@xxxxxxxxx>
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02/16/2007 09:59 AM
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[PCB_FORUM] Speeding up Allegro
Hi folks,
Quick question and I'm pretty sure I've seen this subject floating
around before. Allegro 15.5.1
I'm nearing the end of routing a very large and dense design. I'm down
to cleaning up the power signals (3.3v & gnd.etc) and Allegro is
draggin' big time. What is the easiest way to reduce the time between
mouse clicks when hooking up these large pin count nets? Currently is
about 20 seconds minimum between clicks.
Change the shapes from dynamic to static? I've turned off the on-line
DRC, but that didn't seem to help. I know it's probably something really
obvious, but my brain has turned to mush these last couple days.
Thanx in advance.
Jim S. Wages / SR. PCB Layout Designer:
Cary, NC - H: 919-466-1596 Cell: 919-484-2963
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Dave Seymour, CID+
Catapult Communications Inc.
800 Perimeter Park Dr, Suite A
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