[PCB_FORUM] SI Problem ?
- From: "Naren" <naren@xxxxxxxxxx>
- To: icu-pcb-forum@xxxxxxxxxxxxx
- Date: Wed, 16 Mar 2005 11:51:21 +0530 (IST)
Hi All !
I have circuit in which Test chip is mounted on Test Socket;
It's o/p is going to LVDS Driver.
My problem is i don't have IBIS/Spice models for Testchip & Socket.
But I have RLC (Parasitics) Metrix for both.
can I simulate the signal with above parameters in Allegro Spectaquest 15.2?
--
"Keep looking foreward"
Regards
Naren Thesia
Member CAD
D'GIPRO SYSTEMS PVT. LTD. BANGALORE
-----------------------------------------------------------
To subscribe/unsubscribe:
Send a message to icu-pcb-forum-request@xxxxxxxxxxxxx
with a subject of subscribe or unsubscribe
To view the archives of this list please login at
//www.freelists.org. Our list name is icu-pcb-forum
or go to //www.freelists.org/archives/icu-pcb-forum/
Problems or Questions:
Send an email to icu-pcb-forum-admins@xxxxxxxxxxxxx
Want to post a job listing ? DON'T DO IT HERE!
Better yet, join our jobs listing forum.
SUBSCRIBE: icu-jobs-forum-subscribe@xxxxxxxxxx
POST: icu-jobs-forum@xxxxxxxxxx
-----------------------------------------------------------
Other related posts:
