[PCB_FORUM] Routing layers
- From: "steve kingdon" <steve.kingdon@xxxxxxxxxxxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Thu, 16 Sep 2004 16:04:26 +1200
Hi there,
I am trying to set a constraint that will force signals to be routed on
particular layers.
Basically I want to be able break out to a via on the surface to a
maximum
distance, then only use certain internal layers, and DRCs if someone
inadvertantly
routes on a non preferred layer.
I know how to set this up in a SPECCTTRA do file, but cannot figure out
how to set it
up in Allegro. I think I can use the property MAX_EXPOSED_LENGTH for
the breakout,
but what about the internal layers? And have seen a property
LAYERSET_GROUP in the
documentation, but this property is currently not supported. We are
using 15.2.
Thanks to those who replied to my question on displaying non plated
holes.
Steve.
Steve Kingdon
PCB Designer
Allied Telesyn Research.
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