[PCB_FORUM] Re: Replacing ripped up etch?

  • From: lthemanz <lthemanz@xxxxxxxxx>
  • To: icu-pcb-forum@xxxxxxxxxxxxx
  • Date: Wed, 24 Dec 2008 21:26:47 -0800 (PST)

Folks,
This brings about another issue Michael M mentioned " Besides
seeing some vias and orphaned subnets getting latched to 0V nets or some
other DC Supply shape fills, "
Is there a best practice avoiding this from happening? Even when the dynamic 
shape files being disabled, 'hanging' clines and vias' get attached to 0V nets .

Another thing is sometimes they end up as Dummy Nets (which you could hilite 
and look for) or "Not on a Net". I worry I might have some of this on my 
design, but how do I find them? 

rgds,
Good Food in Penang
Penang Info
Just about Anything and Everything


--- On Tue, 11/11/08, Baumstark Michael-EMB043 <M.Baumstark@xxxxxxxxxxxx> wrote:
From: Baumstark Michael-EMB043 <M.Baumstark@xxxxxxxxxxxx>
Subject: [PCB_FORUM] Re: Replacing ripped up etch?
To: icu-pcb-forum@xxxxxxxxxxxxx
Date: Tuesday, November 11, 2008, 1:35 AM

 Hi Mike C.:

I know this thread is over a week old at this point but I wanted to also
comment about your suggestion for the  "Derive Connectivity"
application.... in response to Dharma's inquiry.

We too have utilized this feature, on occasion, when the nets just don't
quite latch properly to their intended intelligent net, particularly for
some of those design migrations from one CAD tool to an Allegro PCB
layout. 

We have found some strange behavior when "Derive Connectivity" is
performed with the presence of Positive image Shape Fills. Besides
seeing some vias and orphaned subnets getting latched to 0V nets or some
other DC Supply shape fills, some Cline segs will get permanently fused
to the Shape fills that they have been derived to, instead of perhaps
Logical pins that are also in proximity. That was a strange observation
with no ability to remove the Cline segs at a later time, so we have
learned to avoid that particular situation and to be a bit more
judicious into the place and time when Derive Connectivity is executed.

So what we have determined and experienced as the best practice is to
remove OR move (outside of the PCB outline) all Shape fills that are
co-mingled with signal routing. (Dedicated positive plane shape can
stay.) After the Derive Connectivity is performed then the Shape fills
can be moved back into position.


Sincerely yours, 

Michael Baumstark 

Sr. Staff Electrical Engineer / PCB Design, CID+

Motorola - Government & Public Safety 
Physical Design Organization (G&PS - PDO) 
8000 West Sunrise Blvd.  Mail Stop: 8E8 
Plantation, FL USA 33322-9947 
Intra: http://rprc.mot.com  ; http://pcbadvisor.mot.com 
web: http://www.motorola.com 

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Motorola Confidential Proprietary    [      ] 



-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Michael
Catrambone
Sent: Thursday, October 30, 2008 12:56 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Replacing ripped up etch?

Hello,

Did you try running Derive Connectivity? (Tools > Derive Connectivity)

In order for Allegro to see a routed connection it must be snapped to
the center of the pin or via and sometimes during conversions things
round the wrong way which makes the trace not exactly in the center of
the pin or via. "Derive Connectivity" will attempt to resolve these
conditions and maybe it will help with yours.  I would give it a try.

When you run "Derive Connectivity" check the box next to
"Convert Lines
to Connect Lines" the click OK.  (Save a backup of the database of
course before running anything like this)

Hope this helps,
Michael Catrambone
UTStarcom, Inc.


-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Dharma
Kemp-Bresett
Sent: Thursday, October 30, 2008 11:31 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Replacing ripped up etch?

Hi Everyone,
Hopefully this one is as easy to solve as the last question I posted.
:-) 

We have a board file that was converted from pads but has an orcad sch.
We
are now synching the converted brd file with the sch. We had to remove a
bunch of pins from some bgas that were okay in pads but we didn't want
in allegro. I have loaded the netlist and replaced the few symbols that
wouldn't place, or refresh, automatically (due to the "missing
pins")
but now I have a bunch of routes that have become rats. These appear to
be ones that went from the offending symbols to other offending symbols
so its not all rats for these refdes but only a few per refdes with
multiple refdes involved. I have tried everything I can think of in
every combination I can think of to no avail. So the million dollar
question is: Is there a way to get those routes back without having to
go through by hand and make a clip file? Something similar to a
placement file but for routes, maybe?
Thanks in advance,
Dharma

KAW/USA Ltd. 
39 Simon Street, #4
Nashua, NH 03060
603-886-8711 x212
603-881-8763 fax 

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