[PCB_FORUM] Re: Relative prop delay
- From: "Macindoe, Gary" <Gary.Macindoe@xxxxxxx>
- To: icu-pcb-forum@xxxxxxxxxxxxx
- Date: Wed, 18 Apr 2007 14:55:37 -0500
David,
Thanks for the reply.
I have added pin delay properties to some nets in the same Relative
Propagation Delay, and it doesn't seem to be using it in it's
calculations.
I have the tolerance set to 50 mils, and when the net goes beyond that,
it turns red (the pin delays are about 200 mils apart!).
Oh well, I guess it's the old manual way for now.
Our CPU has been matched in the package, but the North Bridge chip has
not.
Regards,
Gary
Gary E. MacIndoe
PCB Design Engineer
Fort Collins, Colorado
amd.com
gary.macindoe@xxxxxxx
________________________________
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of David Greig
Sent: Wednesday, April 18, 2007 11:50 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Relative prop delay
Yes it is possible. You will need to add PIN_DELAY=YES in the [pinprops]
section of allegro.cfg, within orcad.
Far easier to import a delay file into allegro.
Caveat, often the IC package delay (io cell to lead/ball) will have
already been included into static timing models particularly FPGA's with
Timequest, and besides more and more programmable/tuneable io cells
obviate needing such board level precision.
Best Regards
David Greig
______________________________
GigaDyne Ltd
5 Albany Business Centre
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Dunfermline KY12 0RN
United Kingdom
t: +44 (0)1383 624 975
www.gigadyne.co.uk
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________________________________
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Michael
Catrambone
Sent: 18 April 2007 18:11
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Relative prop delay
Gary,
I really don't know if this is possible. We are using both DxDesigner
and ConceptHDL here and only viewed OrCAD schematics but never drove
logic forward to Allegro.
Any OrCAD folks on the forum know if it is possible to embed the Pin
Delay information in the OrCAD schematic library so it is possible to
pass it forward to Allegro?
Sincerely,
Michael Catrambone
UTStarcom, Inc.
Chairman
Cadence Designer Network
CDNLive! Worldwide Web Site: http://www.cdnlive.com
<http://www.cdnlive.com>
Cadence User Community Web Site: http://www.cdnusers.org
<http://www.cdnusers.org>
________________________________
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Macindoe, Gary
Sent: Wednesday, April 18, 2007 11:47 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Relative prop delay
Hey Michael,
Thanks for the reply.
Do you know if schematic package method works in Capture?
Our network is having "issues" (new building), so we can't test it right
now.
Regards,
Gary
Gary E. MacIndoe
PCB Design Engineer
Fort Collins, Colorado
amd.com
gary.macindoe@xxxxxxx
________________________________
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Michael
Catrambone
Sent: Wednesday, April 18, 2007 9:16 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Relative prop delay
Gary,
You will need to add a PIN_DELAY property on the pins of the package
that you have the delays for.
This can be done as Peter described below for ConceptHDL and it can also
be driven thru a 3rd party netlist or added manually to the pins using
Edit > Properties.
The field in CM will remain grayed out until pin pairs are generated
after adding either a Rel Prop or Prop Delay rules or by creating a Pin
Pair.
Here is an example of a 3rd party netlist that can be read in
incrementally using File > Import > Logic (Other Tab)
$PINS
$A_PROPERTIES
PIN_DELAY 376.298 MIL ; U36.AF8
PIN_DELAY 452.969 MIL ; U36.AF6
PIN_DELAY 596.916 MIL ; U36.AK4
Remember to enable Pin Delay checks by opening the Electrical Constraint
Set form accessed inside of Spacing/Physical Constraints. The setting
will be under the Options tab. (Enable "Include in all Propagation
Delays and DiffPair Phase Checks").
Sincerely,
Michael Catrambone
UTStarcom, Inc.
Chairman
Cadence Designer Network
CDNLive! Worldwide Web Site: http://www.cdnlive.com
<http://www.cdnlive.com>
Cadence User Community Web Site: http://www.cdnusers.org
<http://www.cdnusers.org>
________________________________
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Peter Hughes
Sent: Wednesday, April 18, 2007 9:51 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Relative prop delay
Hi Gary,
In order to include the package lengths in a component you need to add
them to the packages section of the schematic symbol. These values will
then appear in the Pin Delay columns.
Rgrds
Peter Hughes,
PCB Designer,
Concurrent Technologies,
4 Gilberd Close,
Newcomen Way,
Colchester,
Essex,
CO4 4WN.
Tel: +44 1206 752626
Fax: +44 1206 751116
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Macindoe, Gary
Sent: 18 April 2007 15:44
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Relative prop delay
Hey guys,
It has reached the point where I have to consider the package length
when matching some nets.
I am using Relative Propagation Delay in CM, and was wondering if anyone
knows how to include the package lengths?
I thought maybe the Pin Delay columns, but they are grayed out.
Any ideas?
Regards,
Gary
Gary E. MacIndoe
PCB Design Engineer
Fort Collins, Colorado
amd.com
gary.macindoe@xxxxxxx
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