[PCB_FORUM] Re: RE : SPAM!!! capture to allegro trouble

  • From: "Peter Hughes" <phughes@xxxxxxxxx>
  • To: <icu-pcb-forum@xxxxxxxxxxxxx>
  • Date: Mon, 27 Feb 2006 08:46:15 -0000

Hi Peter,
 
To match the nets in each group to within 300 mils of each other the 
Delta:Tolerence should be 0 MIL:150 MIL. The tolerance is +/- 150 MILS which 
gives you a range of 300 MILS. Also personally I do not like using the All 
Drivers/All Receivers auto pin pair generation unless there are only 1 of each 
in the net. I believe it is better to specify the pin pairs in the net.
 
Rgrds
 
Peter Hughes,
PCB Designer,
Concurrent Technologies,
4 Gilberd Close,
Newcomen Way,
Colchester,
Essex,
CO4 4WN.
Tel: +44 1206 752626
Fax: +44 1206 751116
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx 
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Peter P.
Sent: 26 February 2006 15:04
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: RE : SPAM!!! capture to allegro trouble
 
I have a problem. I have not posted on the forum yet. Maybe you can help. For 
some reason I cannot remember how to set up trace length matching. What I have 
is a test board. All sockets. I have 4 JTAG lines that go to each one. I need 
to match them within 300 mils only to each socket. I set them up in Constraint 
Manager as groups. Here is a snapshot of it.
-
 
 
Let me know if you can steer me the right way.
 
Peter
 
----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx 
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of westfeldt
Sent: Monday, February 20, 2006 10:24 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: RE : SPAM!!! capture to allegro trouble

Thanks for the method on finding the line number.  I have that saved for next 
time.  I finally solved the problem by isolating the problem to one sch sheet, 
then one sch symbol.  I had already replaced cache on every symbol in the 
design, but just deleting the one symbol and pasting in another in its place 
did the trick.  I could not see anything at all wrong with that part in the 
schematic.


Patrick Westfeldt, Jr.
720-406-0887

-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Jean-Charles TEYSSIER
Sent: Monday, February 20, 2006 9:56 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] RE : SPAM!!! capture to allegro trouble


What is the net name?
See in there is no carriage return in orcad at the end of sig_name, if 
caracters live éçè&µ are used...
You can use vim to find line 1822 (open the file with vim, then type 1582G) 
(carefull, G is case sensitive)
-------- Message d'origine--------
De: icu-pcb-forum-bounce@xxxxxxxxxxxxx de la part de westfeldt
Date: dim. 19/02/2006 05:31
À: icu-pcb-forum@xxxxxxxxxxxxx
Objet : SPAM!!! [PCB_FORUM] capture to allegro trouble

v10.3 capture 15.2 allegro

I have been doing this netlist creation for more than a year now, rarely any 
problems and usually easily found.  But this has me stumped, for many hours.
Error message from capture looks like this:

[Error: Line 1822 in file C:\PWBDAT\CADENCDAT\ALLEGWORK/pstxnet.dat:
          Reference designators inconsistent in xprt and xnet files 
        Detected in function: pstFindInstByOldPathName
Error: Line 1822 in file C:\PWBDAT\CADENCDAT\ALLEGWORK/
pstxnet.dat:
          Error loading the net list file 
        Detected in function: ddbLoadPstXFiles
#133 Error   [ALG0036] Unable to read logical netlist data.]


It's hard to see where line 1822 is, but appears to be just one of the node
line [NODE_NAME C9 2]and I can't see anything wrong.  I would be thrilled if
I could send this capture file to somebody willing to run it and see if they 
get the same error.


Patrick Westfeldt, Jr.
North Boulder Circuit Design
westfeldt_nbcd@xxxxxxxxx
720-406-0887
c 720-272-5822


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