[PCB_FORUM] Re: Prop Delay not seeing all the net
- From: george.h.patrick@xxxxxxxxxxxxxx
- To: icu-pcb-forum@xxxxxxxxxxxxx
- Date: Thu, 3 Mar 2005 09:02:26 -0800
I must have missed the announcement here that the independent ICU was being
dissolved in favor of a Cadence-controlled user group. Hopefully the new
group will reflect the excellent support we all have come to expect from
Cadence.
"May you live in interesting times"
- old Chinese curse
--
George Patrick
Tektronix, Inc.
Central Engineering, PCB Design Group
P.O. Box 500, M/S 39-512
Beaverton, OR 97077-0001
Phone: 503-627-5272 Fax: 503-627-5587
http://www.tektronix.com http://www.pcb-designer.com
It's my opinion, not Tektronix'
-----Original Message-----
From: Dave Seymour [mailto:deseymour-pcb@xxxxxxxxxxxxx]
Sent: Thursday, March 03, 2005 05:31
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Prop Delay not seeing all the net
Mike,
Your knowledge of Allegro is outside the package keepin.
I redid the property and it worked like a champ.
I had tried several combinations, couldn't get it.
Thanks for your help.
Dave.
PS: I went up to the ICU page. I had no idea that the User Group was
being "updated". Congrats on the Chair seat. Say Hi to Carl and Sue.
For any of the other users out there who don't get the the conferences....
Check out:
http://www.cadenceusers.org/
-----Original Message-----
From: Michael.Catrambone@xxxxxxxxxx
Sent: Mar 2, 2005 6:24 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Prop Delay not seeing all the net
Hey Dave.. Howz things..
I believe it is getting confused with the AD:AR
All Drivers/All Receivers in the pin pair field.
The delay rule could be used to DRC total etch length
in 11.X only when you had the pin pair field blank.
DELAY_RULE = ::2000:2500
This would convert to the following rule during uprev:
PROPAGATION_DELAY = L:S:2000:2500
With the PRE_12.0_DELAY_RULE env variable that
you have set it will check the rule the total length of the
net only when you have Longest and Shortest in the
Pin Pair field.
Michael Catrambone
UTStarcom, Inc.
Dave Seymour <deseymour-pcb
03/02/2005 04:57 PM
Please respond to icu-pcb-forum@xxxxxxxxxxxxx
Sent by:
To: icu-pcb-forum@xxxxxxxxxxxxx
cc:
Subject: [PCB_FORUM] Prop Delay not seeing all the net
15.2
Anyone know why a DRC is generated when the entire
net length is correct?
The net length is supposed to be between 2000 and 2500 mils.
Probing the net gives --->Total Etch Length: 2280.31 MIL.
Very good.
When the DRC is probed, only a portion of the net is reported.
Actual value: 1032.65 MIL
Very Bad.
What up with that?
I did check the box for in the user setup for pre 11.x checking.
Thanks for the help.
dave
LISTING: 1 element(s)
< NET >
Net Name: CPU_CLK6
Via Count: 3
Total Etch Length: 2280.31 MIL
Total Manhattan Length: 2257.7 MIL
Percent Manhattan: 101.00%
Pin Type SigNoise Model
--- ---- --------------
R93.2 BI CDSDefaultIO
J5.A13 BI CDSDefaultIO
U4.27 IN CDSDefaultInput
No connections remaining
Properties attached to net
CLASS = CPU_CLK
NET_SPACING_TYPE = CLOCK
NO_GLOSS
MANUAL_ROUTES
PROPAGATION_DELAY = AD:AR:2000 MIL:2500 MIL
LISTING: 1 element(s)
< DRC ERROR >
Class: DRC ERROR CLASS
Subclass: ALL
Origin xy: (2083.30 -790.00)
CONSTRAINT: Propagation Delay
CONSTRAINT SET: PROPAGATION_DELAY
CONSTRAINT TYPE: ATTRIBUTE
Constraint value: AD:AR:2000 MIL:2500 MIL
Actual value: 1032.65 MIL
--
Dave Seymour, CID+
Catapult Communications Inc.
800 Perimeter Park Dr, Suite A
Morrisville, NC 27560
Direct: (919)653-4249
Main: (919)653-4180
Fax: (919)653-4297
Dave.seymour@xxxxxxxxxxxx
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