[PCB_FORUM] ORCAD Layout testpoint question

Hi Everyone,
 I have a customer who is having problems with testpoints in Orcad Layout.
This is beyond my knowledge level with the tool and so I am hoping someone
out there can help us out. I received a copy of the ODB++ and was able to
load it into valor. I am able to select any and all features. I do see a few
"dedicated" test points but those are apparently not the issue. I am
assuming by what I have been told that their software normally goes in and
selects vias which it then "turns into" test points? This is not how allegro
usually works ( where you would run the testpoint procedure before creating
the odb++)so I am stumped. Is anyone aware of this procedure and what could
be the potential problem?

I have excerpted some of his queries below:

The initial question:

"We are having an issue with an old board done in OrCad 9.2 layout. The
flying-probe test house says that the ascii export file is not good, and the
ODB++ file which is valid, won't let them select via's for test points. In
OrCad layout I checked, and the settings are for it to use existing vias as
test points."

Follow up info:

"My understanding is their test software is refusing to use ANY vias, only
pads. The use-via-as-testpoint option is checked in the via stack, and in
the "test point options"."


Any and all help would be appreciated.
Thanks in advance,
Dharma

 



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