[PCB_FORUM] Re: (No Date: Tue, 26 Feb 2008 08:01:01 -0800

Hi Austin,
Thanks so much for the response,
We are using Allegro Performance and prefer to set the values in the
Constraint manager; we have tried but were not successful; Do you know
how
To set the pin pairs and length matching in the constraint manager?; I
would really appreciate any help; as for the 50 mils tol was a value
given by the engineer.
Thanks again 
Soledad

-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Austin Franklin
Sent: Tuesday, February 26, 2008 9:11 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: (No Date: Tue, 26 Feb 2008 08:01:01 -0800

Hi Soledad,

First, a bit on using the Viewlogic front end to pass constraints...

If you are using the Viewlogic/Mentor translator, it should allow you to
pass constraints.  One way, is to use the attributes manager.  Under
project/project settings, the attributes tab, will have a section
"Constraints", and you would click the "Enable Constraints" checkbox,
and
select the pcb layout system you want to use, in your case, Allegro.
Then,
read up on how to use it.

The other way in Viewlogic is simply to attach the appropriate
attributes to
the nets.  You'd need to setup pinpairs between driver and buffer 1 and
driver and buffer 2, and set those into a class/group, then apply a
length
match to that group.

You can also use "virtual pins" in the schematic for the branch point,
or
you can use "T"s in Allegro, which you'll have to setup manually.

One other way, is simply to setup these pinpairs/groups in Allegro
Constraint Manager (which seems to be your preference), and set the
length
matching there.  Are you looking for more details on how, exactly, to do
that?

Do you have at least Allegro Performance (or what ever the new name for
this
is)?

BTW, how come the tolerance of 50 mils was chosen?  Is this a GHz bus?

Regards,

Austin
  -----Original Message-----
  From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx]On Behalf Of Soledad Attia
  Sent: Tuesday, February 26, 2008 11:01 AM
  To: icu-pcb-forum@xxxxxxxxxxxxx
  Subject: [PCB_FORUM] Re: (No Date: Tue, 26 Feb 2008 08:01:01 -0800






  --





  I need some help in setting up the Constraint Manager.  I am using a
third
party schematic tool (ViewLogic) and importing a Tel net file.  How can
I,
from the Allegro (16.01) PCB side, set constraints on an 8-bit address
bus
that feeds two buffer devices?  Each trace in the address bus must be
the
same length from the source to each buffer device and must be within 50
mils
of each other.











  Thanks in advance for your help



  Robert Jones

  PRINTRONIX INC

  714 368-2318
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