[PCB_FORUM] Re: (No Date: Tue, 26 Feb 2008 08:01:01 -0800

 

 

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I need some help in setting up the Constraint Manager.  I am using a
third party schematic tool (ViewLogic) and importing a Tel net file.
How can I, from the Allegro (16.01) PCB side, set constraints on an
8-bit address bus that feeds two buffer devices?  Each trace in the
address bus must be the same length from the source to each buffer
device and must be within 50 mils of each other.  

 

 

 

 

 

Thanks in advance for your help

 

Robert Jones

PRINTRONIX INC

714 368-2318

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