[PCB_FORUM] Re: Negative Shapes: via voiding

Yes, I did this - to the point I was going cross-eyed.

BTW, I'm using dynamic shapes in 15.2.

>>> stanislao_t@xxxxxxxxxxxx 29/10/2004 8:14:49 a.m. >>>
Richard,

Did you set up your assignment table after you made your constraint?
If
you put this property on the net and setup your table correctly it
should work.


Tony Stanislao, Senior PCB Design Engineer
Pannaway Technologies | v: 603.766.5129| e: stanislao_t@xxxxxxxxxxxx 
========================================= 
 

-----Original Message-----
From: richard moffat [mailto:richard.moffat@xxxxxxxxxxxxxxxxxxx] 
Sent: Thursday, October 28, 2004 2:45 PM
To: icu-pcb-forum@xxxxxxxxxxxxx 
Subject: [PCB_FORUM] Negative Shapes: via voiding

Hi

Hoping this hasn't been asked before:

I have set a NET_SPACING_TYPE on a negative shape (plane) to meet
isolation requirements.  The via-to-shape and pin-to-shape spacing
rules
are not being followed.

According to Cadence, the via antipad has priority.  Can I force the
shape to follow the NET_SPACING_TYPE rule?  

(I don't want a positive shape; I think it would kill my design since
it has 22000 vias.)

Cheers,
Richard

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