[PCB_FORUM] Re: Negative Shapes: via voiding

Richard,

You don't say what version of Allegro you are using.  I you're on 15.x, then
I would set the clearance you want in the shape parameters (Shape -> Global
Dynamic Params...).  Under the Clearances tab, set the "Oversize value:"
field for vias to whatever beyond the DRC value that you want.  This will
default to all shapes that you create for your design.  Or, you can set this
oversize value on a per shape basis (Shape -> Select Shape or Void, then
right click on the shape to Parameters...).

If you are still on 14.2, I can't quite remember.  The once in a while that
I would want extra clearance for vias, I would just manually "void circle"
for each one (there never were that many!).

Good luck,

Gary E. MacIndoe
PCB Design Engineer
Advanced Micro Devices, Inc.
Longmont, Colorado




-> -----Original Message-----
-> From: richard moffat [mailto:richard.moffat@xxxxxxxxxxxxxxxxxxx]
-> Sent: Thursday, October 28, 2004 12:45 PM
-> To: icu-pcb-forum@xxxxxxxxxxxxx
-> Subject: [PCB_FORUM] Negative Shapes: via voiding
->
->
-> Hi
->
-> Hoping this hasn't been asked before:
->
-> I have set a NET_SPACING_TYPE on a negative shape (plane) to meet
-> isolation requirements.  The via-to-shape and pin-to-shape spacing rules
-> are not being followed.
->
-> According to Cadence, the via antipad has priority.  Can I force the
-> shape to follow the NET_SPACING_TYPE rule?
->
-> (I don't want a positive shape; I think it would kill my design since
-> it has 22000 vias.)
->
-> Cheers,
-> Richard
->
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