[PCB_FORUM] Re: Negative Shapes: via voiding

Without going positive...

The only way I was able to get this to work was building the
clearance into the anti pad for the hole(via,pin,etc).

Hope this helps.
dave

.



richard moffat wrote:

Hi

Hoping this hasn't been asked before:

I have set a NET_SPACING_TYPE on a negative shape (plane) to meet
isolation requirements.  The via-to-shape and pin-to-shape spacing rules
are not being followed.

According to Cadence, the via antipad has priority. Can I force the
shape to follow the NET_SPACING_TYPE rule? 

(I don't want a positive shape; I think it would kill my design since
it has 22000 vias.)

Cheers,
Richard

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