[PCB_FORUM] Re: Negative Shapes: via voiding
- From: "richard moffat" <richard.moffat@xxxxxxxxxxxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Fri, 29 Oct 2004 09:39:24 +1300
Tried all that :-(
I've attached a pic of what happens:
There are two shapes here. The upper shape has the clearance, with the
oversize value applied. The clearance works for vias touching the shape
but not actually inside the shape. (The white line is the original
shape boundary before it's pulled back from the bottom shape.)
Might get to a barber shop so it'll be harder for me to pull my hair
out.
>>> gary.macindoe@xxxxxxx 29/10/2004 8:25:23 a.m. >>>
Richard,
You don't say what version of Allegro you are using. I you're on 15.x,
then
I would set the clearance you want in the shape parameters (Shape ->
Global
Dynamic Params...). Under the Clearances tab, set the "Oversize
value:"
field for vias to whatever beyond the DRC value that you want. This
will
default to all shapes that you create for your design. Or, you can set
this
oversize value on a per shape basis (Shape -> Select Shape or Void,
then
right click on the shape to Parameters...).
If you are still on 14.2, I can't quite remember. The once in a while
that
I would want extra clearance for vias, I would just manually "void
circle"
for each one (there never were that many!).
Good luck,
Gary E. MacIndoe
PCB Design Engineer
Advanced Micro Devices, Inc.
Longmont, Colorado
-> -----Original Message-----
-> From: richard moffat [mailto:richard.moffat@xxxxxxxxxxxxxxxxxxx]
-> Sent: Thursday, October 28, 2004 12:45 PM
-> To: icu-pcb-forum@xxxxxxxxxxxxx
-> Subject: [PCB_FORUM] Negative Shapes: via voiding
->
->
-> Hi
->
-> Hoping this hasn't been asked before:
->
-> I have set a NET_SPACING_TYPE on a negative shape (plane) to meet
-> isolation requirements. The via-to-shape and pin-to-shape spacing
rules
-> are not being followed.
->
-> According to Cadence, the via antipad has priority. Can I force
the
-> shape to follow the NET_SPACING_TYPE rule?
->
-> (I don't want a positive shape; I think it would kill my design
since
-> it has 22000 vias.)
->
-> Cheers,
-> Richard
->
-> NOTICE: This message contains privileged and confidential
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NOTICE: This message contains privileged and confidential
information intended only for the use of the addressee
named above. If you are not the intended recipient of
this message you are hereby notified that you must not
disseminate, copy or take any action in reliance on it.
If you have received this message in error please
notify Allied Telesyn Research Ltd immediately.
Any views expressed in this message are those of the
individual sender, except where the sender has the
authority to issue and specifically states them to
be the views of Allied Telesyn Research.
Attachment:
plane_clearance.jpg
Description: JPEG image
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