[PCB_FORUM] Re: Logo on Top Etch layer

we did assessment studies before,, comparison...

logo in active layer
-need to be careful, DRC and shorting to active trace.
-takes up space in active area, you loose out for placement and routing.
-you get to have full logo, because the place you can put logo is
normally pretty wide open space and nothing else.
-less visible, if mask is OF other colour(black /blue)  other than
normal green. You cannot see them !!!
- if near active RF trace, not acceptable, potential circuit coupling
may occurs.


logo in silk layer.
-less danger of shorting.
-can be placed anywhere.
-logo sometime gets chopped/cut due to via hole/ pads nearby.
-more visible - white color, regardless of mask colour.
-if logo near Pad,, sometime solder paste printing will have problem
near fine pitch due to extra silk uneven thickness 
-little poorer in terms of quality, normally silk layer cosmetic detail
expectation is less  vs active layer.
-if logo is big, mask out trace info, real nag for debug engineer when
they wanna cut trace.
-larger patch has incomplete printing problem.

choice is yours. for me,, silk is more preferred choice ,, use of etch
has higher risk of potential fatal consequences..
one small mistake can kill the board, but silk,,mmmm maybe a bit ugly or
poor quality or smear, but the board still power up.. 1 less functional
factor to worry about.


CL,Ooi
Cad 





-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Budathoki,
Trilok (GE Infra, Energy)
Sent: Monday, May 29, 2006 7:03 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Logo on Top Etch layer


Gennadity,

Placing Logo in etch layer is not feasible if your board is highly dense
or constrained, I feel it's
unprodictive as a large part of routing area goes untilized.
We placing the logo on non etch layer.

> "Etching layer gives more detail, and because of that the logo can be
smaller."  

.....HOW???? 

- Trilok Budathoki
 GE Energy



 

-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx]On Behalf Of Gennadiy
Kiryukhin
Sent: Friday, May 26, 2006 8:28 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Logo on Top Etch layer


Etching layer gives more detail, and because of that the logo can be 
smaller.
Another interesting thing is that if I create two dummy-net shapes with 
clearance less than my design minimum I also get DRC.
However, if I assign them to GND and then back to dummy, the DRC goes
away.

-Gennadiy

Van Os, Richard (GE Healthcare) wrote:

> Consider placing it on a non etch layer e.g. silk top
>
>-Richard
>
>-----Original Message-----
>From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
>[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Gennadiy
>Kiryukhin
>Sent: Friday, May 26, 2006 8:26 AM
>To: icu-pcb-forum@xxxxxxxxxxxxx
>Subject: [PCB_FORUM] Logo on Top Etch layer
>
>Greetings everybody,
>
>I have a company logo created as a mechanical symbol using shapes on
the
>top etch layer.
>When I place the symbol onto my board it gives me a DRC error because
>some of the shapes are too close to each other (even though the
same-net
>DRC is turned off). To remove the DRC error, after I place the symbol,
I
>manually reassign the shape to some other valid net like GND and after
>that I reassign it back to a dummy net (back to what it was). That
>clears my DRC errors.
>
>Does anybody know of any way to create a symbol such that the DRC error
>would not be in the first place. I just hate to go and reset the net
>assignment every time I place the symbol.
>
>Gennadiy Kiryukhin
>Development Engineer
>ATSI
>
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>  
>


-- 

Gennadiy Kiryukhin
Development Engineer
ATSI
8157 US Route 50
Athens, OH 45701
Phone: (740) 592-2874
Fax (740) 594-2875

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