[PCB_FORUM] Re: Length matching for DDR - was - RE: Re:Allegro V6.01 Constraint Manager

Hi Richard,

> I gave you some examples and I gave you some reasons.  You said
> you were receptive to new ideas but apparently not.

Of course I'm open to new information/understanding and the ensuing
discourse, which is why I've spent the time to read what you wrote and read
the information at the links you provided.  The examples you gave, so far,
haven't provided any information that supported your claim for tighter
length match constraints for the T branches.  In fact, the TI reference
showed they were the same (though lacked any analysis or explanation for
where they got their numbers from).

> There is more to life than designing from timing diagrams, and
> simulations do not always simulate real life and definitely not EMC.

No doubt there is more to life than that but not when you need to provide
proper constraints for high speed designs.

In my experience, simulators are quite good these days, especially for SI
and high speed design (at least up to the low to mid GHz which is the limit
of my experience).  If an SI simulation is inaccurate, and you're using a
good simulator, there is something wrong with the parameters of the
simulation.

> I think you have to be careful giving advice on tolerances.

I agree and I am ;-)

I don't really want to argue, that's not the point.  I just want the
information presented to be substantiated and accurate, and if it isn't, to
know that as well.  No matter the source of the information.

Regards,

Austin

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