[PCB_FORUM] Length matching for DDR - was - RE: Re: Allegro V6.01 Constraint Manager

Hi Richard,

> Seriously, I would like to give examples, but I can't.  We are under
> strict NDAs with silicon vendors such as Marvel and Broadcom.

As am I...

> Trust me, they exist.

Not that I've run across, but I haven't used every chip they make.  If you
can reference a document, I can get it.

I go by what I personally have designed and tested, and I have done
simulations that show contrary to your belief.  Which brings up a good point
that I believe was overlooked.  Not everyone has the ability to use
simulation to see what "works", so they must rely on some other methodology
to try to determine how to get a somewhat engineered number for length
matching.  What I've pointed out not only gives a basic understanding of the
problem but a viable solution for most cases, certainly in the 1GHz and
under range.  Above that, in lieu of having hard constraints from a vendor,
simulation is pretty much mandatory IMO.

> I stand by my original sentence:  "I think you have to be careful giving
advice on tolerances."

I *am* careful ;-)  What I've provided is a basic understanding of the
problem, as well as some examples of how to solve it.  I haven't said
"length match your design to 250 mils".  What I want to provide is the
information for someone be able to understand the issue and to be able to
derive the answer on their own.

> > I have read all the books on this topic by Brooks, Johnson and Ritchie.
> > I've also given talks on this very subject, and written papers and
> > application notes for various vendors.  I am an EE, and I do exactly
this
> > stuff (designing high speed designs, up to the mid GHz ranges)
routinely.

> Ditto on all the above, apart from app notes.

OK...then, I'd expect you would be able to provide some level of
substantiation to the T issue we disagree on.  There should be *some*
empirical evidence (like a simulation) that supports this...

> > I'd be more than happy to learn
> > something I didn't know, but my direct experience differs from what you
are
> > saying...but that doesn't mean I couldn't be wrong.

> I'd like to send datasheets, but I can't.  See
>  http://focus.ti.com/lit/an/spraac5f/spraac5f.pdf ,
> page 19.  Not exactly our designs, but the same idea.
> It is to force reflections to cancel.

I looked at that page/diagram.  It doesn't say a thing about making the
length matching from the T to the destination tighter than from the source
to the destination, at least that I saw. They only provide source to
destination length match numbers.  Did I perhaps miss something?

When I find something in a datasheet and app notes (like a length match
number that seems out of whack), I ask for an explanation from the vendor.
The responses I've gotten typically are that they just gave that number as a
very optimistic number, or they can't give any empirical explanation.  An
optimistic number makes sense when they provide hard numbers (and isn't
necessarily "wrong" per se), but that doesn't mean you couldn't do an
analysis (simulation or what have you) and come up with "better" numbers.
I'd bet that the 100 mils they spec in this app note is from another source,
like a Micron or Intel app note, which is probably for module DDR.  100 mils
seems really "aggressive" for this length match, IMO.  But, if I am going to
change something that a vendor recommends in their documentation, I always
run it by them.

Here is an Intel app note:

http://int.xscale-freak.com/XSDoc/IXP4xx/30526102.pdf

See p. 87.  It gives a length match for DDR for the data group (DQ/DQS/DM)
of +/- .25ns, or +/- 250ps, or +/- 1.5".  For the control group +/- .6ns or
+/- 3.6".  This is for DDR-266, not for DDR2 etc., which will have tighter
tolerances, by a factor of 2-4...but even at 2-4, it's a far cry from 100
mils!  Even if you tighten it up by 4x, it's 375 mils for data and 900 mils
for control.  Also, there is no mention of using a tighter tolerance for T
to destination.  They also provide simulation results.

Note, they are length matching to a bit over %10 of the frequency for the
data group (266 x 2 = 532 = 1.9ns 250ps/1900ps = .13.  The control group is
similar.  So, using, what I call an aggressive %2 of the frequency to see if
they are even ballpark, those results would certainly be acceptable, though
an overconstraint.  My use of %2 was simply to illustrate the point that a
50 mil length match seemed very aggressive, even by an aggressive standard,
in Solidad'd case, and gave me cause for ask where it came from.

> > > > My point is, where do these length match numbers come from?

> > > The come from the people who design the silicon.  They are not
> > > just random numbers.

> > Well, that's simply not true.  Length match numbers are design
dependant,
> > and though there is information in the datasheets that you can derive
the
> > information from, typically, there is nothing in a datasheet that says
> > "length match to +/- 100 mils".  There exceptions as I stated like
certain
> > TMDS datasheets for example, but it is not routinely specified.

> I'm not telling the truth?   Careful here.  See the above example, page
19.

That length match numbers "come from the people who design the silicon"
isn't necessarily true.  Most vendors do not provide hard length match
numbers.  If a vendor does provide hard length match numbers, it is very
situation dependant, and won't necessarily be correct in all cases.  They
don't necessarily know how you are going to be using the device(s), what you
are interfacing to, and what material you are using, and what frequency you
are running at.  In some circumstances, sure, they provide the numbers, and
they're good to go.  In (most IME) other cases, it's typically up to the
engineer to do the analysis and provide these constraints.

<snip>

> > > Read what I wrote about t-based topologies, and exactly where you need
> > > tight tolerances in certain areas.

> > How "tight"?  How do you derive the number you use?  What's the
equation?

> There is no equation as such.  The figures are in the datasheets.  See the
above.

Sometimes, sure.  But, what about devices that don't have such "figures" in
the datasheets?  How do you go about determining this?  The answer is,
analysis and/or simulation.  But, in most cases less than 1GHz, again, I
contend that a proper length match rule for source to destination will
render constraining the T to destination "tighter" moot (I don't disagree it
should be minimized though), and using %2 of the frequency will give you a
good idea of what will more than likely work, if not be rather aggressive
and an overconstraint.

If you would like to continue this off-list, I'd be more than happy to.

Regards,

Austin

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