[PCB_FORUM] Re: Length matching for DDR
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Fri, 29 Feb 2008 10:19:07 +0530
Can you send me the link url.
Thanks
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Alan Williams
Sent: Thursday, February 28, 2008 8:35 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Length matching for DDR
Hi,
Unfortunately I deleted all the previous messages from this thread when
I came in this morning (there were 27 or so!!)....
....so I don't really know what you were discussing...
However if I get a gist and people are looking for guidelines for DDR
length matching (not DDR2, or QDR..) Then I just did a board and spend
lots of time and effort trying to get it right. I constrainted my design
to the guidelines put out by micron in TN-46-14.. You should find it on
their website, if you don't let me know I'll hunt out the url for you.
I must mention the board is being manufactured as we speak, so for all I
know it won't work, but I'm confident it will.
If I'm completely off topic just ignore me!
Cheers,
Al.
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Austin Franklin
Sent: 28 February 2008 14:53
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Length matching for DDR - was - RE: Re: Allegro
V6.01 Constraint Manager
Hi Richard,
> > I'd like to send datasheets, but I can't. See
> > http://focus.ti.com/lit/an/spraac5f/spraac5f.pdf , page 19. Not
> > exactly our designs, but the same idea.
> > It is to force reflections to cancel.
> I looked at that page/diagram. It doesn't say a thing about making
> the
length
> matching from the T to the destination tighter than from the source to
> the destination, at least that I saw. They only provide source to
> destination length match numbers. Did I perhaps miss something?
Actually, I did miss something. Their diagram confused me, they used
rectangles to indicate the segment lengths (yet they say "length A to
C", when they really mean A + C), instead of lines. But, none the less,
I believe I understand it now, and they specify:
"Length B should match length C within 100 mils."
Which is apparently the T to destination...so they do specify
this...but...
"Length A to C and A to B should match within 100 mils within ADDR_CTRL
net class."
The A segment is the same for both A to C and A to B, which means it is
only the B and C segments that length match to the 100 mils...so stating
that B should length match C to within 100 mils is redundant.
The proof:
A to C = A + C, A to B = A + B, so they want the following:
100 = ABS((A + C) - (A + B))
100 = ABS(C - B)
So:
ABS((A + C) - (A + B)) = ABS(C - B)
for simplicity let's remove ABS for now...and since no order of
precedents exist in addition/subtraction:
Let's substitute - (A + B) = - A - B in the equation:
A + C - A - B = C - B
A - A makes A drop out so we are left with:
C - B = C - B
...and means the two constraints are equal, which means they aren't
constraining the T to destination tighter than the overall length match.
Unless I made a mistake somewhere...but I think I got that right.
Best Regards,
Austin
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- References:
- [PCB_FORUM] Re: Length matching for DDR
- From: Alan Williams
Other related posts:
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- » [PCB_FORUM] Re: Length matching for DDR
- » [PCB_FORUM] Re: Length matching for DDR
- [PCB_FORUM] Re: Length matching for DDR
- From: Alan Williams