[PCB_FORUM] Re: Length matching for DDR

Hi Randy,

<snip> all good references...

> David Price at
> Born To Route, for T-route, length match of the address T
> segments to data routes

Do you have more info on this reference?  I know David, I know his web
site...is this a reference to something he wrote, or from informal
discussions?

> All boards had no issues.

I would expect nothing less ;-)

> Look for the results during the Beijing Olympics, the designs were for a
ultra-HD
> (16x HD) video camera I worked on for Micron.

A story on one video board I worked with...having nothing to do with your
design, but having to do with DDR and video.  I was working with a reference
design board provided by TI for their Discovery 3000 chipset.  We were
finding problems in the video...  Writing some more stringent tests for the
board, specifically the DDR memory tests were failing.  I eventually asked
them for the layout file, which luckily was an Allegro file.  I found that
the constraints on the DDR were incorrectly done.  The board had two
component DDRs (DDR2 if I remember right).  One had the clock and address
lines length matched correctly (and that DDR worked OK), the other had the
clock the same length as the other DDR, and the address lines matched
amongst themselves, but not to the clock that went to that chip.  That was
the chip that was getting DDR errors.  Obviously, they thought it worked
before releasing it, but in fact, it had an issue.

Regards,

Austin

-----------------------------------------------------------
To subscribe/unsubscribe: 
Send a message to icu-pcb-forum-request@xxxxxxxxxxxxx
with a subject of subscribe or unsubscribe

To view the archives of this list go to 
http://www.freelists.org/archives/icu-pcb-forum/

Problems or Questions:
Send an email to icu-pcb-forum-admins@xxxxxxxxxxxxx
-----------------------------------------------------------

Other related posts: