[PCB_FORUM] Re: Is there a way to step and repeat placement for identical circuits on the same PCB?

Hi Austin,

- Are bga ball connected together in netlist?
- How do you copy clines? With an increment like ix 50 iy 50 ?
- Staring in 15.7, allegro tries to "snap" to pins when copying clines... it can be usefull or borying... I dont know how to avoid it. One idea: move component s away, copy the clines then get back the components: the snap function should not works in this case. 

Regards,

Jean-Charles

Austin Franklin a écrit :

Hi Jean-Charles,

I'm only copying clines, not vias.  I have four BGAs, and I routed one, and
tried to copy the clines (top layer) and got the error.  But...I can copy
the clines on the inner layers, as they are connected to vias.  So, it has
something to do with pads/pins vs vias.

Regards,

Austin


-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx]On Behalf Of JCharles
TEYSSIER
Sent: Sunday, May 24, 2009 4:30 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Is there a way to step and repeat placement for
identical circuits on the same PCB?


Franklin,

do you tried to move clines and vias with ix 0 0 increment? This way
allegro assign clines to right nets.
Maybe some components are not at the proper place, so you have to
complete components swap..
One other thing: do you have planes on others layers? Vias try to attach
to planes when copied.... I but planes offboard then move ix 0 0 vias
to, reconect to right signals. Then back planes in board.
Maybe a dbdoctor can also help...

Regards,

Jean-Charles

Austin Franklin a écrit :

Hi Jean-Charles,



- As you say, routing can be copied. Symbols can be also copied.


Well, I can copy the routing...but I get DRC errors when I drop

it on the

other components "top line to SMD pin spacing".  The two components I am
copying the routing from/to are on the same grid.  If I route

directly from

the pins of the 2nd component, the routing is fine.  What seems to be
happening, is the clines aren't taking on the net names that

the pins are

assigned to.  What am I doing wrong?  I know I've done this

before with no

problem.  I'm using 15.7.

Regards,

Austin
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