[PCB_FORUM] Re: Impedance controlled line widths

The Shape Mesh Size will affect the impedance calculations.  Check
http://sourcelink.cadence.com/docs/db/kdb/2002/Oct/11051900.html and
http://sourcelink.cadence.com/docs/db/kdb/2002/Feb/11008448.html
<http://sourcelink.cadence.com/docs/db/kdb/2002/Feb/11008448.html> .
This is old, but still applicable, at least in 15.5.1.
 

Regards, 
Charlie 


 

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[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Ed Caldwell
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Subject: [PCB_FORUM] Re: Impedance controlled line widths



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"Jean Bratton" <jean.bratton@xxxxxxxxxxxxxx> 
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08/29/2007 10:11 AM 
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Hi folks, 
We have a design with impedance rules built in at the schematic level.
The stackup appears to be correctly defined as provided to us, but
Allegro is not calculating the trace widths at the same width as the
stackup indicates they should be. The impedance value appears to be the
prevailing rule, not the trace width we have set up in the constraints.
If we delete the impedance property, we can get the board to route with
the trace widths we specify, but we're wondering if there's a way to
change the priority...to have it look at what the design rules specify
for trace width rather than what the impedance rule would automatically
define. 
  
Also, does anyone know of a good impedance calculator online? The one we
used to use isn't set up for a board as thick as this one is, so we need
another. We need to know which is accurate, the stackup provided to us,
or the calculations Allegro is making. 
Thanks for any insight, 
Jean 
  
Jean Bratton 
Sr. Printed Circuit Designer 
Freedom CAD Services, Inc. 
603-864-1349 
jean.bratton@xxxxxxxxxxxxxx <mailto:jean.bratton@xxxxxxxxxxxxxx>  
Visit us at http://www.freedomcad.com <http://www.freedomcad.com/>  
  

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