[PCB_FORUM] Re: Impedance controlled line widths

Hope this is what you mean: the impedance property is overruling the physical 
type.
 
Set environment variable acon_no_impedance_width in the etch category.
 
Off topic, but is anyone else getting fabs telling you that your track widths 
for microstrips are off because they are
calculating using the latest Polar tool? I use a couple of BEM, MOM and several 
different 3D full wave tools that are in closer
agreement to each other than the values the fab shops are reporting back.
 
Best Regards
 
David Greig
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GigaDyne Ltd
5 Albany Business Centre
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United Kingdom
t: +44 (0)1383 624 975
www.gigadyne.co.uk
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  _____  

From: icu-pcb-forum-bounce@xxxxxxxxxxxxx 
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Jean Bratton
Sent: 29 August 2007 15:10
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Impedance controlled line widths



Hi folks,

We have a design with impedance rules built in at the schematic level. The 
stackup appears to be correctly defined as provided
to us, but Allegro is not calculating the trace widths at the same width as the 
stackup indicates they should be. The impedance
value appears to be the prevailing rule, not the trace width we have set up in 
the constraints. If we delete the impedance
property, we can get the board to route with the trace widths we specify, but 
we're wondering if there's a way to change the
priority.to have it look at what the design rules specify for trace width 
rather than what the impedance rule would
automatically define. 

 

Also, does anyone know of a good impedance calculator online? The one we used 
to use isn't set up for a board as thick as this
one is, so we need another. We need to know which is accurate, the stackup 
provided to us, or the calculations Allegro is
making.

Thanks for any insight,

Jean

 

Jean Bratton

Sr. Printed Circuit Designer

Freedom CAD Services, Inc.

603-864-1349

 <mailto:jean.bratton@xxxxxxxxxxxxxx> jean.bratton@xxxxxxxxxxxxxx

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