[PCB_FORUM] Re: Impedance controlled line widths

Dave,

Point taken, my comments were for sub GHz designs. And I would agree with 1 GHz 
+ designs that considerable verification is required at the assembly level to 
prove the product, and this type of verification is much better than a summary 
of bare PCB test results from a fabricator. However, I don't believe that 
complete reliance on a modelling tool is the answer, unless you deal with only 
1 fab shop and have a real good characterization of any variables related to 
their processing.

Again, only my opinion. Please do set me straight if I'm off base (or 
completely wrong).

Thanks,
Dave






> 
> From: "David Greig" <david@xxxxxxxxxxxxxx>
> Date: 2007/08/29 Wed AM 10:41:01 CDT
> To: <icu-pcb-forum@xxxxxxxxxxxxx>
> Subject: [PCB_FORUM] Re: Impedance controlled line widths
> 
> Dave,
> 
> With all respect, few fab shops measure, or indeed are able to measure, 
> impedance at 1GHz+. Most use tools like Polar CITS or
> similar. With tr/tf in the order of 50ps to 500ps most of their means of 
> verification are becoming increasingly irrelevant.
> 
> Where it matters I specify materials sometimes down to vendor PN's, including 
> masks, and take into account etch and lamination
> processing.
> 
> 
> Best Regards
>  
> David Greig
> ______________________________
> GigaDyne Ltd
> 5 Albany Business Centre
> Gardeners Street
> Dunfermline KY12 0RN
> United Kingdom
> t: +44 (0)1383 624 975
> www.gigadyne.co.uk
> ______________________________
> 
> -----Original Message-----
> From: icu-pcb-forum-bounce@xxxxxxxxxxxxx 
> [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Dave Schaefer
> Sent: 29 August 2007 16:17
> To: icu-pcb-forum@xxxxxxxxxxxxx; icu-pcb-forum@xxxxxxxxxxxxx
> Subject: [PCB_FORUM] Re: Impedance controlled line widths
> 
> Jean / David,
> 
> I always consult with my fab shop, as their processes impact the impedances 
> yielded. I have had many designs which have required
> material / feature adjustment when transitioning from prototype fabricator to 
> volume fabricator.
> 
> Here's my basic process:
> - evaluate my impedance requirements using available calculators / cad tools, 
> factor in any other requirements to come up with a
> desired stackup.
> - send the critical design details to the fabricator for comment & 
> recommendation (stackup, materials, trace widths &
> clearances, etc.).
> - modify my design to satisfy design intent and fabricator capabilities.
> 
> There's no CAD tool or calculator that contains "process effective 
> dielectric" constants for every PCB vendor.
> 
> Hth,
> Dave
> 
> > 
> > From: "David Greig" <david@xxxxxxxxxxxxxx>
> > Date: 2007/08/29 Wed AM 09:54:06 CDT
> > To: <icu-pcb-forum@xxxxxxxxxxxxx>
> > Subject: [PCB_FORUM] Re: Impedance controlled line widths
> > 
> > Hope this is what you mean: the impedance property is overruling the 
> > physical type.
> >  
> > Set environment variable acon_no_impedance_width in the etch category.
> >  
> > Off topic, but is anyone else getting fabs telling you that your track 
> > widths for microstrips are off because they are calculating using the 
> > latest Polar tool? I use a couple of BEM, MOM and several different 3D full 
> > wave tools that are in closer agreement to each
> other than the values the fab shops are reporting back.
> >  
> > Best Regards
> >  
> > David Greig
> > ______________________________
> >  
> > GigaDyne Ltd
> > 5 Albany Business Centre
> > Gardeners Street
> > Dunfermline KY12 0RN
> > United Kingdom
> > t: +44 (0)1383 624 975
> > www.gigadyne.co.uk
> > ______________________________
> >  
> > 
> >   _____
> > 
> > From: icu-pcb-forum-bounce@xxxxxxxxxxxxx 
> > [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Jean Bratton
> > Sent: 29 August 2007 15:10
> > To: icu-pcb-forum@xxxxxxxxxxxxx
> > Subject: [PCB_FORUM] Impedance controlled line widths
> > 
> > 
> > 
> > Hi folks,
> > 
> > We have a design with impedance rules built in at the schematic level. 
> > The stackup appears to be correctly defined as provided to us, but 
> > Allegro is not calculating the trace widths at the same width as the 
> > stackup indicates they should be. The impedance value appears to be 
> > the prevailing rule, not the trace width we have set up in the 
> > constraints. If we delete the impedance property, we can get the board to 
> > route with the trace widths we specify, but we're
> wondering if there's a way to change the priority.to have it look at what the 
> design rules specify for trace width rather than
> what the impedance rule would automatically define.
> > 
> >  
> > 
> > Also, does anyone know of a good impedance calculator online? The one 
> > we used to use isn't set up for a board as thick as this one is, so we 
> > need another. We need to know which is accurate, the stackup provided to 
> > us, or the calculations Allegro is making.
> > 
> > Thanks for any insight,
> > 
> > Jean
> > 
> >  
> > 
> > Jean Bratton
> > 
> > Sr. Printed Circuit Designer
> > 
> > Freedom CAD Services, Inc.
> > 
> > 603-864-1349
> > 
> >  <mailto:jean.bratton@xxxxxxxxxxxxxx> jean.bratton@xxxxxxxxxxxxxx
> > 
> > Visit us at  <http://www.freedomcad.com> http://www.freedomcad.com
> > 
> >  
> > 
> > 
> > This correspondence and any attachments are considered confidential. 
> > If you are not the intended recipient, please notify Freedom CAD 
> > Services, Inc. immediately by either replying to this message or by sending 
> > an email to operations@xxxxxxxxxxxxxx; please
> destroy all copies of this message and any attachments. Thank you.
> > 
> > --
> > 
> > Virus scanned by Lumison.
> > 
> > 
> > 
> 
> Dave Schaefer
> dave.schaefer@xxxxxxx
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> 
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> 

Dave Schaefer
dave.schaefer@xxxxxxx
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