[PCB_FORUM] Re: Enviroment Variable

Julian,
If you use the mapping mode = refdes, you should be able to force it to
match exactly. When there are multiples of the exact same part, there
are times that the mapping algorithm can get confused. You can also have
multiple potential refdes on a given part in the topology. Just separate
them by a ",". 
John


-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Julian
Ungureanu (jungurea)
Sent: Monday, March 19, 2007 11:22 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Enviroment Variable

The connections are the same; the tool thinks that I should swap U2 with
U3.

Julian 

-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Schwartz,
Jerome
Sent: Monday, March 19, 2007 9:15 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Enviroment Variable

I haven't had that problem.
If one or more of the connections is missing the topology generally
fails. 


Jerry


-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Julian
Ungureanu (jungurea)
Sent: Monday, March 19, 2007 11:52 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Enviroment Variable

I'll give you an example:
You have a CPU (U10) and a 5 memory chips (U1, U2, U3, U4 and U5).
You route the ADDRESS from  U10 to U1, U2, U3, U4,      and U5 in this
order.
You want to reuse this topology for another CPU-mem block. When you
apply the topology to this new circuit, You get a ET error because the
tools thinks that you should route the equivalent of U10  to U1, U3, U2,
U4, U5.
Although the traces and the memory chips are the same you are getting an
error.
Because the mapping is not the way you think it should be but the way
Allegro wants.

Julian

-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Schwartz,
Jerome
Sent: Monday, March 19, 2007 8:43 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Enviroment Variable

What exactly do you mean by mapping errors? 


Jerry


-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Julian
Ungureanu (jungurea)
Sent: Monday, March 19, 2007 11:28 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Enviroment Variable

Will that fix mapping errors?

Julian 

-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Schwartz,
Jerome
Sent: Monday, March 19, 2007 7:58 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Enviroment Variable

 set update_ecset_refdes


Jerry


-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx]
Sent: Monday, March 19, 2007 10:54 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Enviroment Variable

Hi All,

Does anyone out there remember what the environment variable you can set
is, so that when you renumber a PCB the ECSet topologies will renumber
as well.

Rgrds
 
Peter Hughes,
PCB Designer,
Concurrent Technologies,
4 Gilberd Close,
Newcomen Way,
Colchester,
Essex,
CO4 4WN.
Tel: +44 1206 752626
Fax: +44 1206 751116

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