[PCB_FORUM] Re: DRC

Yes, old bugs reappears some times (specially on shapes... and gerbers(import)) looks like someone ask for a different behavior for a command, cadence does it and brake something related (recent fillet's problems is an exemple) 
I have found an other thing very dangerous:
15.7, not yet in 16.x.
If you describe a spacing via2someting_else to a value (say 1mm) but test via to 0.5mm (why not?), then test via value take precedence on the greater value. 
This is how allegro works and hotline say it should not be corrected....

Jean-Charles

William Billereau a écrit :


Hello again.

If it can help someone we found something interesting here:
We have 2 big boards (really big) with a lot of electrical constraints and special shapes (one is called horse shoe ;-)
When we want to update DRCs, the system runs with 50% of processor, and then crashes or terminates without updating DRCs or saying that system is out of memory …. 

We send the biggest one to Cadence.
They replied that it took less than 5 minutes to update and everything is OK. 

We tried to do it in another service, it runs, less than few minutes..
We suspected that the setup was wrong… I tried to find, removing SKILL, variable environment, … It works when I remove a environment variable with PATH with some setup…
I found that if I remove our env file, it works but I cannot find where exactly.
I have a look to Sourcelink and found a solution given for 15.2 with a PCR for 15.5.
So it cannot be this because we are in 15.7, test were done in 16.01. The PCR should be present in these releases. 

I try nevertheless: I removed the use_accurate_delay_calculation.

And … it works!

(never mind: we successfully asked for a more powerful computer! ;-)

Some bugs seem to reappear at Cadence...

Sourcelink said:

*Update DRC & Database Check run until system is out of memory*

*Error Message:*

Memory Error...

*Problem statement:*
When I run update *drc* or database check with *drc* enabled, the *process* runs and runs 

until I get a memory error. What can I do to fix this?

*Solution:*
In this case, the problem was cause by the variable use_accurate_delay_calculation
being enabled. This has been reported in PCR 799814 and fixed in the 15.5 release. 

Workaround:

1) Disable use_accurate_delay_calculation from Setup > User Preferences >

Signal_analysis and then run Update *DRC* or database check.

*/William Billereau/*/
CERN group TS / DEM
1211 Genève 23 Suisse///

        

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Tel: (+4122) 76 73403// //
mail to: william.billereau@xxxxxxx <mailto:william.billereau@xxxxxxx>///


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