[PCB_FORUM] Re: DGND/AGND merge point

  • From: "Ritter, Alan" <Alan.Ritter@xxxxxxxxxx>
  • To: icu-pcb-forum@xxxxxxxxxxxxx
  • Date: Thu, 21 Apr 2005 09:34:47 -0400

This is one of the classic problems...our local workaround is fine if you
use negative plane layers, and goes something like this:

The negative plane consists of two classes, one etch (call it subclass
"GND") and one anti-etch (call it "GNDSEP").  

On the etch, create your shapes for GND and AGND, attach them to the
respective nets and let Allegro generate the thermal reliefs, antipads,
etc., as appropriate.  Leave a 25-mil or so gap between the GND and AGND
shapes.

On the anti-etch, lay down a 25-mil (or narrower if you prefer) LINE (not
CLINE) that traces the boundary between your GND and AGND shapes.  We also
add a 50-mil line just inside the perimeter of the board, as well, to keep
copper planes away from the cut edge.

Now, for the trick:  LEAVE A GAP in the AGND/DGND separation line.  Pick the
location per your customer's requirements (usually either at the A/D
converter, or at the power connector).  When you create artwork for the
plane layer, make sure that you have it set up as a NEGATIVE layer.  Turn on
the pads and shapes for the etch class, and the lines for the anti-etch
class.  Click the "suppress shape fill" option and generate artwork.  This
will generate the antipads and thermals for pins/vias and the separation
barriers.

We have used this workaround (and it IS a workaround) for quite a while.  It
keeps good track of AGND/DGND connectivity but does NOT guarantee that the
separation/junction between the two is correct...you, as designer, have to
verify that by viewing the Gerber files out the far end of the process.

Yes, it's a kludge...but it works...

/s/jar (alan.ritter@xxxxxxxxxx)
        http://www.mtritter.org

Quite often, a board contains both AGND and DGND and the customer asks us
to connect them together on a single point on the board, like GND pin of a
connector.
 
Does anybody know how to do it in Allegro without generating DRCs errors?





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