[PCB_FORUM] Re: Copper balancing "thieving dots"
- From: "Mike Finczak" <mike@xxxxxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Wed, 22 Sep 2004 17:28:38 -0400
Mitch,
The idea was to plan stack-ups so that copper layers would
be symmetrical around the centreline (z axis) of the board.
Individual cores may have solid copper on one side and signal
traces on the other during the PCB manufacturing process, but
when booked together, the copper distribution would be
symmetrical
to within 10 percent.
e.g. Total Copper Area
top --> 70 sq in
plane --> 150 sq in
sig2 --> 20 sq in
<--- z axis
centreline
sig2 --> 18 sq in
plane --> 149 sq in
bot --> 77 sq in
The company I worked for was a multi-billion dollar telecom.
(before and after the meltdown) They had entire departments
researching PCB design standards, in order to maximize board
yield and minimize costs at every stage of the manufacturing
process.
I once had an enlightening discussion with one our board
suppliers.
He told me to think of bare PCB cost in terms of junking rates.
If you insist on running a 4 thou track, four thou away from a
large plane, down the length of the board, the number junked
boards increases to produce the same quantity. The board shop
charges you more, but does not complain to you, as they do not
want to appear un-corporative.
Regards,
Mike Finczak
CopperCAD Design
www.CopperCAD.com
905-488-8958
-----Original Message-----
From: Mitch S. Morey [mailto:cadpro2k@xxxxxxxxxx]
Sent: September 22, 2004 5:01 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Copper balancing "thieving dots"
Hi Mike,
1) So if layer 3 was a SOLID copper pwr/gnd plane, layer 2 (if that was
the core -1 manufactured with it had to be within 10%, right? As well as
the layer pair symmetrical to it in the stackup. Doesn't that imply that
you copper poured all the other layers? I'd think so.
2) What happened to the company you "used to work for"? Are they out of
business? Never heard of that practice.
Good day.
>
> Mitch,
> I used to work for a company that had insisted that the total
> copper area per layer be symmetrical within +/-10 percent
> vertically within the stack-up.
>
> e.g. Total copper area on layer 1 (top minus 1) would
> have to be within 10 percent of layer 7 (bottom plus 1)
>
> Their manufacturing group believed that boards would be less
> likely to warp when heated in the IR oven, if the entire PCB
> had a uniform distribution of copper in both the x-y and z axis.
> Even distribution of copper on all layers also helps the PCB
> manufacturers, weather they ask for it or not.
>
>
> Regards,
> Mike Finczak
> CopperCAD Design
> www.CopperCAD.com
> 905-488-8958
>
> -----Original Message-----
> From: Mitch S. Morey [mailto:cadpro2k@xxxxxxxxxx]
> Sent: September 22, 2004 12:57 PM
> To: icu-pcb-forum@xxxxxxxxxxxxx
> Subject: [PCB_FORUM] Re: Copper balancing "thieving dots"
>
>
> Hi Mark,
>
> Dumb question... Why not just copper pour (GND plane) the top/bottom
> layers, to have the same result? Be a lot quicker to me. Am I missing
> something?
>
> Good day.
>
>> -----Original Message-----
>> From: Mark Salberg [mailto:msalberg@xxxxxxxxxxxx]
>>
>> Does anybody know of an easy way to create (in Allegro) copper
>> balance
>
>> thieving dots? We are instructed to balance all boards in the
>> database
>
>> and not to give fab free rein in their placement.
>> We are currently adding 100 mil shapes on 200 mil spacing...manually.
>>
>> Thanks,
>> Mark
>>
>>
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