[PCB_FORUM] Re: Constraint manager xnets

Austin,
I was not aware of the type of interface, on my original response.
If using DDR the topology, is to place series termination closest to the
memory device, even though it is a bidirectional  source synchronous
bus, and yes your are correct, it is better to center the data around
the strobes, the strobes should be the target, this will improve your
timing margins.
I believe DDRII DIM MODULES already have series termination on the
modules.
Regarding VTT termination, it is ok to ignore under CM, as long as you
have setup driver/receiver under CM "constraint manager" it will
automatically create the correct pin pair from driver to receiver,
regardless of how many passive you have in between or after
driver/receiver, as typically used by double series termination, or VTT
-Patrick

-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Austin Franklin
Sent: Friday, January 27, 2006 11:11 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Constraint manager xnets

Hi Patrick,

> Note: you need to assigned a length restriction on the short side of
the
> series termination, reason, is that you really do not want to add
length
> at the short side of the series termination, any extra trace delay
> should be added at the receiver side of the signal.

That is design dependant, and there is an exception.  Keep in mind, he
is
talking about the DQS/DQ/DM group, not the address control group.  For
the
address/control group, the series terminator is close to the source and
your
suggestion is correct.  In the case of the data groups, the series
terminator is either one at each end, where your suggestion is
correct...applied to both ends, or one kept midway between the two
drivers,
and therefore there really is no short side.

He also didn't say if he was using VTT, and if so, he needs to set-up
the
match group using pinpairs, not nets, and set-up a match group from the
ASIC/FPGA to the DDR.  If there is more than one DDR on those nets, each
has
it's own match group, and then some critical topology issues have to be
addressed as well).  Then set-up another match group from the ASIC/FPGA
to
the VTT.  The one to VTT is far less critical, and can be typically 2x
the
one to the DDR.

If there is only one DDR per data signal, then you tap the VTT through
the
DDR pin.  If you have multiple DDRs sharing the data signals, then you
tap
the VTT right at the branch point (same goes for the control group).
Keep
the branch point close to the DDR, and use scheduling and virtual pins
to
enforce the topology.

Most of this is assuming this is component DDR, not module DDR.  Rules
are
slightly different for using memory modules.

Regards,

Austin
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