[PCB_FORUM] Re: Constraint Region in 16.01

please use display -constraint and make a pick on the pwr_gnd cline. I
would expect to see this feedback noting the row "Region-NetClass". This
is informing you the line width at the pick point is being resolved at
the RC level.
 
 
 
 


________________________________

        From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Joe.witten
        Sent: Wednesday, May 20, 2009 10:04 PM
        To: icu-pcb-forum@xxxxxxxxxxxxx
        Subject: [PCB_FORUM] Re: Constraint Region in 16.01
        
        
        I've got the shape assigned and works as far as getting the
4.75mil traces to route at 4mils.  But this is making the PWR_GND route
at 4mils also.  That's why I thought by adding the Region-Class PWR_GND
and assigning the referenced Cset of PWR_GND I'd get a 20mil trace.
        This is what the Display constraints window is showing:
         
         
         

                -----Original Message-----
                From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Ed Hickey
                Sent: Wednesday, May 20, 2009 4:01 PM
                To: icu-pcb-forum@xxxxxxxxxxxxx
                Subject: [PCB_FORUM] Re: Constraint Region in 16.01
                
                
                Is the Region shape assigned to the Region Constraint
Object?
                 
                In the PCB Editor, select the Region shape with the
shape select command then check the options panel field "Assign to
Region" for the Region constraint object. 
                 
                One other tip - use the Display - Constraint command to
determine how Allegro resolves physical and spacing constraints
                 
                1 pick on the cline for physical info; window around 2
clines for spacing
                 
                 
                 
                 


________________________________

                        From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Joe.witten
                        Sent: Wednesday, May 20, 2009 12:57 PM
                        To: icu-pcb-forum@xxxxxxxxxxxxx
                        Subject: [PCB_FORUM] Constraint Region in 16.01
                        
                        

                        I am trying to set a physical rule that allows a
4mil trace in a BGA region, but still forces a 20mil trace on all power
nets.  I've got physical constraints set up for BGA=4mils and
PWR_GND=20mils.  This still wants to route at mils.  What am I doing
wrong?

                         

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