[PCB_FORUM] Re: Constraint Manager

I think you could create CSET out of one pin pair (XL) and then apply for a group, but you do not need to create pin pairs just use all drivers/all receivers constraint since resistor to Vtt is not a driver and you have simple point to point topology (L). 

cheers,
Robert

Chew Wang wrote:

Hi all,
I have DDR connections coming to DDR DIMM (J3) from processor (U1) thru the 
series termination. It also has the VTT end termination.
I have defined the net as Xnet, as it makes my length matching simpler. Now 
the problem is:

While using Constraint manager, I need to define pin pair for the match
group. Because I am not bothered regarding the length from DIMM to end (VTT) 
terminations.

So I create pin pairs from U1 to J3.But I need to repeat it for all 64 bit
databus,13bit address,3 clk's etc... which is very hectic work.

Is there any process to make my work simpler..

Regards
Chew.Wang




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